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quad-sharc ? dsp multiprocessor family ad14060/ad14060l rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . performance features adsp-2 1060 core processor ( 4) 480 mflops peak, 32 0 mflops sustaine d 25 ns instr u ction rate, single- cycle instruction executioneac h of four processors 16 mbit share d sram (interna l to sharcs ) 4 gigawords addressable off - module memo ry twelve 40 mby t e/s link ports ( 3 per shar c) four 40 mbit/s independent s e rial ports (one from each sharc) one 40 mbit/s common serial port 5 v an d 3.3 v o p eratio n 32-bit single pr ecision and 40- bit extended precision ieee floating point data formats, or 32-bit fixe d point data format ieee jtag stan dard 1149.1 te st access port and on-chip emulation packaging features 308-le ad cera mic quad flatp a ck (cqfp) 2.05" (52 mm ) body size cavit y up o r do wn, c o nfigurable low profile, 0.160" height hermetic 25 mil ( 0 .65 m m ) lead pitch 29 grams (t ypical) jc = 0.36 c/w func tio n a l block di agram cp a sport 1 eboot, lboot, bm s cs tim exp link 1 link 3 link 4 irq 2? 0 flag 2, 0 em u clkin r eset spor t 0 tck, tms, trst flag 1 flag 3 sha rc_ a (i d 2? 0 = 1) link 0 link 2 link 5 tdo link 0 link 2 link 5 tdi link 0 link 2 link 5 tdi eboot, lboot, bm s em u clkin r eset spor t 0 trst tms, tck, trst tms, tck, flag 1 flag 3 , cpa sport 1 tdo sharc_d (id 2? 0 = 4) cs tim exp link 1 link 3 link 4 irq 2?0 flag 2, 0 a d 14 060/ a d 14 060 l cp a sport 1 tdi link 0 link 2 link 5 tdo eboot, lboot, bm s em u clkin r eset spor t 0 flag 1 flag 3 tdi cpa sport 1 sharc_c (id 2? 0 = 3) sharc_b (id 2? 0 = 2) cs tim exp link 1 link 3 link 4 irq 2?0 flag 2, 0 sharc bus ( addr 31?0 , data 47?0 , ms 3-0 , rd, wr, page, adrclk, sw, ack, sbts, hbr, hbg, redy, br 6? 1 , rpba, dmar 1.2 , dmag 1.2 ) eboot, lboot, bm s em u clkin r eset spor t 0 tck, tms, trst flag 1 flag 3 tdo cs tim exp link 1 link 3 link 4 irq 2? 0 flag 2, 0 00667-001 fi g u r e 1 . general description the ad14060/ad14060l q u ad-s h a r c is t h e f i rs t in a famil y of h i g h p e r f or m a nc e d s p m u lt ipro c e ss or m o d u l e s . t h e c o re of th e m u l t i p r o cess o r is th e ads p -21060 ds p micr o c o m p u t e r . th e ad14060/ad1 4060l has the hig h es t p e r f o r ma n c e-t o -den si ty and l o we st c o st- t o - p e r f or manc e r a t i o s of an y in i t s cl ass . i t is ide a l fo r a p plic a t io n s r e q u ir in g hig h er le v e l s o f p e r f o r ma n c e an d / or f u nc t i on a l it y p e r u n it ar e a . the ad14060/ad14060l ta k e s ad van t a g e o f th e b u il t-in m u l t i p r o ces s in g f e a t ur es o f th e ads p -21060 t o ac hieve 480 p e ak mflo ps wi t h a sin g le c h i p typ e in a sin g le p a c k a g e . t h e on - c h i p sr a m of t h e d s p s prov i d e s 1 6 m b it s of on - m o d u le s h a r e d s r am. th e com p let e s h a r e d b u s (48 da t a , 32 addr ess) is a l s o b r o u g h t o f f- m o d u le fo r in t e r f acin g w i t h e x p a ns i o n me m o r y or ot he r p e r i ph e r a l s . the ads p -2106 0 link p o r t s a r e in t e r c o n nec t e d t o p r o v ide dir e c t co mm uni c a t io n a m on g t h e fo ur s h arc s , as w e l l as hig h sp e e d of f - mo d u l e ac c e ss . i n te r n a l ly , e a ch s h a r c has a dire c t l i n k p o r t co nnec t io n. e x ter n al l y , eac h s h ar c has a t o ta l o f 120 mb yt es/s lin k p o r t b a ndw id t h . m u l t i p r o ces s o r p e r f o r ma n c e is enhan c e d wi t h em b e dde d p o wer a nd g r o u nd plan es, m a tch e d i m p e dance i n terco nne c t , an d o p ti m i z e d si gn a l r o u t i n g le n g th s a n d se pa ra ti o n . th e full y te ste d a nd re a d y - to - i ns e r t m u lt i p ro c e ss or a l s o s i g n i f i c an t l y r e d u ces bo a r d sp ace .
ad14060/ad14060l rev. b | page 2 of 48 table of contents specifications ..................................................................................... 3 electrical characteristics (3.3 v, 5 v supply) ............................ 3 explanation of test levels ........................................................... 4 timing specifications ....................................................................... 5 memory readbus master ........................................................ 8 memory writebus master ....................................................... 9 synchronous read/writebus master ................................... 10 synchronous read/writebus slave ...................................... 12 multiprocessor bus request and host bus request .............. 13 asynchronous read/writehost to ad14060/ad14060l .15 three-state timingbus master, bus slave, hbr , sbts ..... 17 dma handshake ........................................................................ 18 absolute maximum ratings .......................................................... 27 esd caution ................................................................................ 27 pin configuration and function descriptions ........................... 28 pin function descriptions ........................................................ 30 detailed description ...................................................................... 34 architectural features ................................................................ 34 shared memory multiprocessing ............................................. 34 off-module memory and peripherals interface .................... 36 link port i/o ............................................................................... 38 serial ports .................................................................................. 38 program booting ........................................................................ 38 host processor interface ........................................................... 39 direct memory access (dma) controller ............................. 39 applications ..................................................................................... 40 development tools .................................................................... 40 quad-sharc development board ......................................... 40 other package details ................................................................ 40 target board connector for emulator probe ......................... 40 output drive currents .............................................................. 42 power dissipation ...................................................................... 42 test conditions ........................................................................... 43 assembly recommendations .................................................... 45 pcb layout guidelines .............................................................. 46 mechanical characteristics ....................................................... 47 additional information ............................................................. 47 outline dimensions ....................................................................... 48 ordering guide .......................................................................... 48 revision history 12/04rev. a to rev. b format updated..................................................................universal changes to specifications section.................................................. 3 changes to development tools section ...................................... 40 changes to target board for emulator probe section .............. 40 changes to figure 27...................................................................... 42 updated outline dimensions ....................................................... 48 changes to ordering guide .......................................................... 48 10/97rev. 0 to rev. a 4/97revision 0: initial version
ad14060/ad14060l rev. b | page 3 of 48 specifications table 1. recommended operating conditions b grade k grade parameter min max min max unit v dd supply voltage (5 v) 4.75 5.25 4.75 5.25 v supply voltage (3.3 v) 3.15 3.6 3.15 3.6 v t case case operating temperature ?40 +100 0 +85 c electrical characteristics (3.3 v, 5 v supply) table 2. 5 v 3.3 v parameter case temp test level test condition min typ max min typ max unit v ih1 high level input voltage 1 full i @ v dd = max 2.0 v dd + 0.5 2.0 v dd + 0.5 v v ih2 high level input voltage 2 full i @ v dd = max 2.2 v dd + 0.5 2.2 v dd + 0.5 v v il low level input voltage 1 , 2 full i @ v dd = min 0.8 0.8 v v oh high level output voltage 3 , 4 full i @ v dd = min, i oh = ?2.0 ma 4 4.1 2.4 v v ol low level output voltage 3 , 4 full i @ v dd = min, i ol = 4.0 ma 4 0.4 0.4 v i ih high level input current 5 , , 6 7 full i @ v dd = max, v in = v dd max 10 10 a i il low level input current 5 full i @ v dd = max, v in = 0 v 10 10 a i ilp low level input current 6 full i @ v dd = max, v in = 0 v 150 150 a i ilpx4 low level input current 7 full i @ v dd = max, v in = 0 v 600 600 a i ozh three-state leakage current 8 , , , 9 10 11 full i @ v dd = max, v in = v dd max 10 10 a i ozl three-state leakage current 8 , 12 full i @ v dd = max, v in = 0 v 10 10 a i ozhp three-state leakage current 12 full i @ v dd = max, v in = v dd max 350 350 a i ozlc three-state leakage current 13 full i @ v dd = max, v in = 0 v 1.5 1.5 ma i ozla three-state leakage current 14 full i @ v dd = max, v in = 1.5 v (5 v), 2 v (3.3 v) 350 350 a i ozlar three-state leakage current 10 full i @ v dd = max, v in = 0 v 4.2 4.2 ma i ozls three-state leakage current 9 full i @ v dd = max, v in = 0 v 150 150 a i ozlsx4 three-state leakage current 11 full i @ v dd = max, v in = 0 v 600 600 a i ddin supply current (internal) 15 full iv t ck = 25 ns, v dd = max 1.4 2.92 1.0 2.2 a i ddidle supply current (idle) 16 full i v dd = max 800 760 ma c in input capacitance 17 , 18 25c v 15 15 pf 1 applies to input and bidirectional pins: data 47-0 , addr 31-0 , rd , wr , sw , ack, stbs , irq y 2-0 , flagy0, flag1, flagy2, hbg , csy, dmar1 , dmar2 , br 6-1 , rpba, cpa y, tfs0, tfsy1, rfs0, rfsy1, lyxdat 3-0 , lyxclk, lyxack, eboota, lboota, ebootbcd, lbootbcd, bmsa , bmsbcd , tms, tdi, tck, hbr , dr0, dry1, tclk0, tclky1, rclk0, rclky1. 2 applies to input pins: clkin, reset , trst . 3 applies to output and bidirectional pins: data 47-0 , addr 31-0 , ms 3-0 , rd , wr , page, adrclk, sw , ack, flagy0, flag1, flagy2, timexpy, hbg , redy, dmag1 , dmag2 , br 6-1 , cpa y, dto, dty1, tclk0, tclky1, rclk0, rc lky1, tfs0, tfsy1, rfs0, rfsy1, lyxdat 3-0 , lyxclk, lyxack, bmsa , bmsbcd , tdo, emu . 4 see the section for typical drive current capabilities. output drive currents 5 applies to input pins: stbs , irq y 2-0 , hbr , cs y, dmar1 , dmar2 , rpba, eboota, lboota, ebootbcd, lbootbcd, clkin, reset , tck. 6 applies to input pins with internal pull-ups: dr0, dry1, tdi. 7 applies to bused input pins with internal pull-ups: trst , tms. 8 applies to three-statable pins: data 47-0 , addr 31-0 , ms 3-0 , rd , wr , page, adrclk, sw , ack, flagy0, flag1, flagy2, redy, hbg , dmag1 , dmag2 , bmsa , bmsbcd , tdo, emu . (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id 2-0 = 001 and another adsp-2106x is not requesting bus mastership. hbg and emu are not tested for leakage current.) 9 applies to three-statable pins with internal pull-ups: dty1, tclky1, rclky1. 10 applies to ack pin when pulled up. (note that ack is pulled up internally with 2 k ? during reset in a multiprocessor system, when id 2-0 = 001 and another adsp-2106x is not reques ting bus mastership.) 11 applies to bused three-statable pins with internal pull-ups: dt0, tclk0, rclk0. 12 applies to three-statable pins with internal pull-downs: lyxdat 3-0 , lyxclk, lyxack. 13 applies to cpa y pin. 14 applies to ack pin, when the keeper latch is enabled. 15 applies to v dd pins. conditions of operation: each processor is executing radix-2 fft butterfly with instruction in cache, one data operand i s fetched from each internal memory block, and on e dma transfer is occurring fr om/to internal memory at t ck = 25 ns. 16 applies to v dd pins. idle denotes ad14060/ ad14060l state during execut ion of idle instruction. 17 applies to all signal pins. 18 guaranteed, but not tested.
ad14060/ad14060l rev. b | page 4 of 48 explanation of test levels test level i 100% production tested. 1 ii 100% production tested at 25c, and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and analysis, and characterization testing on discrete sharcs. v parameter is typical value only. vi all devices are 100% production tested at 25c, and sample tested at temperature extremes. 1 link and serial ports: all are 100% tested at die level prior to assembly. all are 100% ac tested at module le vel; link 4 and serial 0 ar e also dc tested at the module level. see the section. timing specifications
ad14060/ad14060l r e v. b | pa ge 5 o f 4 8 timing specifications this da t a sh e e t r e p r es en ts p r o d uc t i o n -r e l e a s e d sp e c if ic a t ion s f o r th e ad1406 0 (5 v), a n d f o r th e ad14060l ( 3 .3 v). the ads p -21060 die co m p onen ts ar e 100% t e s t ed , a nd t h e as s e m b led ad1 4060/ad14060 l uni t s a r e a g a i n ext e n s i v e l y te ste d a t sp e e d and ac ro ss te m p e r a t u r e. p a r a me t r ic l i mi ts we re es ta b l ish e d f r o m the ads p -21 060 c h a r ac t e r i za tio n f o l l o w ed b y f u r t h e r desig n and a n al ysis o f th e ad14060 /ad14060l p a c k ag e char ac ter i st ic s . the sp e c if ic a t ion s a r e b a s e d on a clki n f r e q ue n c y o f 40 mh z (t ck = 2 5 ns ) . t h e dt d e r a t i ng a l l o w s sp e c i f i c a t i o ns a t ot he r clki n f r e q uencies (wi t h i n t h e mini m u m to m a x i m u m ran g e of t h e t ck s p e c if ica t ion; s e e t a b l e 3). d t is t h e dif f er en ce b e tw e e n t h e ac t u a l cl kin p e r i o d and a cl ki n p e r i o d o f 25 n s : dt = t ck ? 25 n s u s e t h e exac t t i min g i n fo r m a t i o n g i v e n. d o n o t a t t e m p t t o d e r i ve p a r a me te r s f r om t h e a d d i t i on or su bt r a c t i o n of ot he r s . w h i l e ad di t i o n o r sub t r a c t ion w o u l d y i eld m e a n in g f u l r e su l t s fo r a n indivi d u a l de vice, t h e va lues g i ven i n t h is d a t a she e t r e f l e c t s t at i s t i c a l v a r i at i o n s a n d w o r s t c a s e s . c o n s e q u e nt l y , o n e c a n n ot me an i n g f u l ly a d d p a r a me te rs to d e r i ve l o nge r t i me s . s w itching c h a r a c te r i s t i c s sp e c if y h o w the p r o c ess o r c h a n g e s i t s sig n als. th e us e r has n o con t r o l o v er this timingcir c u i t r y ext e r n al t o t h e p r o c es s o r m u s t b e desig n e d fo r co m p a t ib i l i t y wi t h t h es e s i g n a l char ac ter i st ic s . s w i t ch ing char ac ter i st ic s s p e c if y w h a t t h e p r o c es s o r do es in a g i v e n cir c u m s t an c e . th e us er ca n als o us e sw i t chin g cha r ac t e r i s t ics t o ens u r e t h a t an y ti m i n g r e q u i r em en t o f a de v i ce co nn ect e d t o t h e p r oces so r ( s u c h a s me mor y ) i s s a t i s f i e d. ti m i n g r e q u i r e m e n t s ap p l y t o s i g n a l s t h at a r e c o nt r o l l e d b y ci r c ui tr y e x t e rn al t o th e p r oces s o r , s u c h a s th e da ta i n p u t f o r a r e ad o p era t io n. t i mi n g r e q u ir e m e n ts gu a r a n t e e t h a t t h e p r o c es s o r o p era t es co r r e c t l y wi t h o t h e r de vices. (o/d) = op en dra i n (a/d) = a c ti v e dr i v e table 3. clock input 40 mhz (5 v) 40 mhz (3.3 v) parameter m i n m a x m i n m a x unit clock input timing requirements: t ck c l k i n p e r i o d 2 5 1 0 0 2 5 1 0 0 n s t ck l c l k i n w i d t h l o w 7 9 . 5 n s t ck h c l k i n w i d t h h i g h 5 5 n s t ck rf clkin rise/fall ( 0 .4 v to 2.0 v) 3 3 ns cl k i n t ckh t ckl t ck 00667-011 fi g u r e 2 . c l o c k i n p u t
ad14060/ad14060l r e v. b | pa ge 6 o f 4 8 table 4. r e set 5 v 3.3 v parameter m i n m a x m i n m a x unit reset timing requirements: t wr s t reset pulse width lo w 1 4 t ck 4 t ck n s t srst reset setup before clkin high 2 14 + dt/2 t ck 14 + dt/2 t ck ns 1 appli e s a f t e r t h e p o wer- up seq u en ce i s com p l e t e . at po wer- up, t h e proc es sor s i n t e rn a l ph a s e - locke d lo op req u i r es n o m o r e t h a n 2000 clkin c y cles whi l e re se t is low, a ssum i n g st a b le v dd a n d clkin (n o t i n cludi n g st a r t - u p t i m e of t h e e x t e rn a l c l ock o s ci lla t o r ) . 2 only r e quired if m u ltiple ad sp-2106x s must come out of reset synchronou s t o cl kin with progr am counters (pc) equal (that is, f or a si md sy st em ). n o t r e q u i r ed for multiple adsp-2106xs communicatin g over the shared b u s (through the ext e rnal port), becau s e the bu s arbitration logic automatic a lly syn c h r on i z es i t se lf a f t e r res e t . cl k i n r eset t wrst t srst 00667-012 fi g u r e 3 . r e s e t table 5. i n terrupts 5 v 3.3 v p a r a m e t e r m i n m a x m i n m a x u n i t interrupts timing requirements: t sir irq 2-0 setup before clkin high 1 18 + 3 dt/4 18 + 3 dt/4 ns t hir irq 2-0 hold before clkin high 1 11.5 + 3 dt/4 11.5 + 3 dt/4 ns t ipw irq 2-0 pulse width 2 2 + t ck 2 + t ck n s 1 on ly r e q u i r ed f o r irq x recognition in the f o l l owing cycle. 2 appli e s on ly i f t sir a n d t hir re quire m e n t s are no t me t. cl k i n ir q 2? 0 t ip w t hi r t si r 00667-013 f i gure 4 . interrupts
ad14060/ad14060l r e v. b | pa ge 7 o f 4 8 table 6. timer 5 v 3.3 v parameter m i n m a x m i n m a x unit timer switching ch aracteristic: t dt ex clkin high to ti mexp 16 16 ns cl ki n timexp t dtex t dtex 00667-014 f i gure 5. ti mer table 7. flags 5 v 3.3 v parameter m i n m a x m i n m a x unit flags timing requirements: t sf i flag2-0 in setup before clkin high 1 8 + 5 dt/16 8 + 5 dt/16 ns t hfi flag2-0 in hold after clkin hig h 1 0.5 ? 5 dt/16 0.5 ? 5 dt/16 ns t dwrf i flag2-0 in delay after rd / wr low 1 4.5 + 7 dt/16 4.5 + 7 dt/16 ns t hfi w r flag2-0 in hold after rd / wr de-assert ed 1 0 . 5 0 . 5 n s switching ch aracteristics: t df o flag2-0 ou t delay after clkin hi gh 17 17 ns t hfo flag2-0 ou t hold after clkin hi gh 4 4 ns t df oe clkin high to f lag2-0 ou t e n a b l e 3 3 n s t df od clkin high to f lag2-0 ou t d i s a b l e 1 5 1 5 n s 1 fla g i n put s t h a t meet t h e se s e t u p a n d h o ld t i m e s a f fect con d i t i o n a l i n st ruct i on s i n t h e f o l l owi n g i n st ruct i on cycle. cl ki n fl a g 2 ? 0 ou t flag output t dfo t hfo t dfo clkin rd, wr flag input t sfi t hfi t hfiwr t dwrfi fl a g 2 ? 0 in t dfoe t dfod 00667-015 fi g u r e 6 . f l a g s
ad14060/ad14060l r e v. b | pa ge 8 o f 4 8 memor y read bus m a ster u s e t h es e sp e c if ica t ion s fo r asy n chr o n o us in t e r f acin g t o m e m o r i es (a n d m e m o r y -ma p p e d p e r i ph era l s) w i t h o u t r e fer e n c e t o c l kin. th es e sp ecif ic a t io n s a p p l y w h en the ad14060/ad14060l is t h e b u s mast er ac ces s in g ext e r n al m e m o r y s p ace . th e s e s w i t c h in g c h a r ac t e r i s t ics als o a p p l y fo r b u s mas t er sy n c hr o n o u s r e ad/wr i t e timin g (s e e t h e s y n c hr on o u s re ad/w r i t e bus m a s te r s e c t i o n ) . i f t h e s e t i m i ng re qu i r e m e n t s are me t , t h e s y nch r onou s re a d / w r i te t i m i ng c a n b e i g nore d ( a nd v i c e ve r s a ) . table 8. s p ecification s 5 v 3.3 v parameter m i n m a x m i n m a x unit timing requirements: t dad ad d r ess, delay to data valid 1 , 2 17.5 + dt + w 17.5 + dt + w ns t drld rd low to data valid 1 11.5 + 5 dt/8 + w 11.5 + 5 dt/8 + w ns t hda data hold from address 3 1 1 n s t hdr h data hold from rd high 3 2 . 5 2 . 5 n s t daak ack delay from address 2 , 4 13.5 + 7 dt/8 + w 13.5 + 7 dt/8 + w ns t dsak ack delay from rd low 4 7.5 + dt/2 + w 7.5 + dt/2 + w ns switching ch aracteristics: t drha ad d r ess hold after rd high ?0.5 + h ?0.5 + h ns t darl addres s to rd low 2 1.5 + 3 dt/8 1.5 + 3 dt/8 ns t rw rd pulse width 12.5 + 5 dt/8 + w 12.5 + 5 dt/8 + w ns t rw r rd high to wr , rd , dmag x low 8 + 3 dt/8 + hi 8 + 3 dt/8 + hi ns t sadadc address setup before adrclk h i gh 2 ?0.5 + dt /4 ?0.5 + dt /4 ns w = number of wait s t ates s p ecif ied in wa it regis t er t ck . hi = t ck , i f a n a d dre s s h o ld cycl e o r bu s i dle cyc l e occur s , a s speci f i e d i n w a it r e gi st er; ot h e rwi s e, h i = 0. h = t ck , i f a n a d dre s s h o ld cycl e occ urs a s sp eci f i e d i n w a i t regi st er ; ot h e rwi s e, h = 0. 1 d a t a dela y/ set u p: user m u st m e et t da d , t dr l d , or syn c h r on ous speci f icat ion , t ssdati . 2 for ms x, sw , bms , t h e fa lli n g edge i s re fer e n c ed. 3 d a t a h o ld: us er m u st m eet t hda , t hdr h , or s y nchronous s p ec if ication, t hdati . see t h e sect i o n f o r t h e ca lcu l a t i o n of h o l d t i m e s gi ven ca pa ci t i ve a n d dc l o a ds. sy st em h o l d ti m e ca lc ula t i o n exa m ple 4 a c k de la y/s et up: u s er m u st m e et t dsak , t daak , or s y nchronous s p ecif ication, t sac k c . addre s s msx , s w bm s w r , d ma g ack dat a adrclk (out) t drha t darl t drld t hdrh t dsak t rwr t daak t dad t hda t sadadc t rw 00667-016 rd f i gure 7 . memo r y r e a d b us ma ster
ad14060/ad14060l r e v. b | pa ge 9 o f 4 8 memor y writebus master u s e t h es e sp e c if ica t ion s fo r asy n chr o n o us in t e r f acin g t o m e m o r i es (a n d m e m o r y -ma p p e d p e r i ph era l s) w i t h o u t r e fer e n c e t o c l kin. th es e sp ecif ic a t io n s a p p l y w h en the ad14060/ad14060l is t h e b u s mast er ac ces s in g ext e r n al m e m o r y s p ace . th e s e s w i t c h in g c h a r ac t e r i s t ics als o a p p l y fo r b u s mas t er sy n c hr o n o u s r e ad/wr i t e timin g (s e e t h e s y n c hr on o u s re ad/w r i t e bus m a s te r s e c t i o n ) . i f t h e s e t i m i ng re qu i r e m e n t s are me t , t h e s y nch r onou s re a d / w r i te t i m i ng c a n b e i g nore d ( a nd v i c e ve r s a ) . table 9. s p ecification s 5 v 3.3 v parameter m i n m a x m i n m a x unit timing requirements: t daak ack delay from address, selects 1 , 2 13.5 + 7 dt/8 + w 13.5 + 7 dt/8 + w ns t dsak ack delay from wr low 1 8 + dt /2 + w 8 + dt /2 + w ns switching ch aracteristics: t dawh ad d r ess, selects to wr de-asserted 2 16.5 + 15 dt/16 + w 16.5 + 15 dt/16 + w ns t dawl ad d r ess, selects to wr low 2 2.5 + 3 dt/8 2.5 + 3 dt/8 ns t ww wr pulse width 12 + 9 dt/16 + w 12 + 9 dt/16 + w ns t ddwh data setup before wr high 6.5 + dt/2 + w 6.5 + dt/2 + w ns t dwha ad d r ess hold after wr de-asserted 0 + dt/16 + h 0 + dt/16 + h ns t dat r wh data disable after wr de-asserted 3 0.5 + dt/16 + h 6.5 + dt/16 + h 0.5 + dt/16 + h 6.5 + dt/16 + h ns t wwr wr high to wr , rd , dmag x low 8 + 7 dt/16 + h 8 + 7 dt/16 + h ns t ddwr data disable before wr or rd low 4.5 + 3 dt/8 + 1 4.5 + 3 dt/8 + 1 ns t wde wr low to data enabled ?1.5 + dt /16 ?1.5 + dt /16 ns t sadadc address, selects to adrclk hig h 2 ?0.5 + dt /4 ?0.5 + dt /4 ns w = number of wait s t ates s p ecif ied in wa it regis t er t ck . h = t ck , i f a n a d dre s s h o ld cycl e occ urs, a s sp eci f i e d i n w a i t regi st er ; ot h e rwi s e, h = 0. i = t ck , if a bus idl e c y cl e occurs , a s s p ec if ie d in wait regist er; otherwise, i = 0. 1 a c k de la y/s et up: u s er m u st m e et t daak , t dsak , or s y nchronous s p ecif ication, t sac k c . 2 for ms x, sw , bms , t h e fa lli n g edge i s re fer e n c ed. 3 se e t h e sect i o n for t h e ca lcu l a t i o n of h o ld t i m e s gi ven ca pa ci t i ve a n d dc loa d s . syst em ho ld ti m e ca lcula t i o n exa m p le rd, dmag ack data wr a ddre s s msx, sw bms ad rcl k (out) t dawh t daak t dsak t wde t ddwh t wwr t ddwr t datrwh t sadadc t ww t dawl t dwha 00667- 017 f i gur e 8 . memo r y w r it e bus m a st er
ad14060/ad14060l rev. b | page 10 of 48 synchronous read/writebus master use these specifications for interfacing to external memory systems that require clkinrelative timing or for accessing a slave adsp 2106x in multiprocessor memory space. these synchronous switching characteristics are also valid during asynchronous memor y reads and writes (see the memory readbus master and memory writebus master sections). when accessing a slave adsp-2106x, these switching characteristics must meet the slaves timing requirements for synchronous read/writes (see the synchronous read/writebus slave section). the slave adsp-2106x must also meet these bus master timing requirements for data and acknowledge setup and hold times. table 10. specifications 5 v 3.3 v parameter min max min max unit timing requirements: t ssdati data setup before clkin 3 + dt/8 3 + dt/8 ns t hsdati data hold after clkin 4 ? dt/8 4 ? dt/8 ns t daak ack delay after address, ms x, sw , bms 1 , 2 13.5 + 7 dt/8 + w 13.5 + 7 dt/8 + w ns t sackc ack setup before clkin 2 6.5 + dt/4 6.5 + dt/4 ns t hackc ack hold after clkin ?0.5 ? dt/4 ?0.5 ? dt/4 ns switching characteristics: t dadro address, ms x, bms , sw , delay after clkin 1 8 ? dt/8 8 ? dt/8 ns t hadro address, ms x, bms , sw , hold after clkin ?1 ? dt/8 ?1 ? dt/8 ns t dpgc page delay after clkin 9 + dt/8 17 + dt/8 9 + dt/8 17 + dt/8 ns t drdo rd high delay after clkin ?2 ? dt/8 +5 ? dt/8 ?2 ? dt/8 +5 ? dt/8 ns t dwro wr high delay after clkin ?3 ? 3 dt/16 +5 ? 3 dt/16 ?3 ? 3 dt/16 +5 ? 3 dt/16 ns t drwl rd / wr low delay after clkin 8 + dt/4 13.5 + dt/4 8 + dt/4 13.5 + dt/4 ns t sddato data delay after clkin 20 + 5 dt/16 20.25 + 5 dt/16 ns t dattr data disable after clkin 3 0 ? dt/8 8 ? dt/8 0 ? dt/8 8 C dt/8 ns t dadcck adrclk delay after clkin 4 + dt/8 11 + dt/8 4 + dt/8 11 + dt/8 ns t adrck adrclk period t ck t ck ns t adrckh adrclk width high (t ck /2 ? 2) (t ck /2 ? 2) ns t adrckl adrclk width low (t ck /2 ? 2) (t ck /2 ? 2) ns w = number of wait states specified in wait register t ck . 1 for ms x, sw , bms , the falling edge is referenced. 2 ack delay/setup: user must meet t daak , t dsak , or synchronous specification, t sackc . 3 see the section for the calculation of hold times given capacitive and dc loads. system hold time calculation example
ad14060/ad14060l rev. b | page 11 of 48 clkin adr cl k addre s s sw ack (in) page rd data (out) wr t hackc t ssdati t hsdati data (in) t dadcck t dadro t drdo t dattr t sackc t drwl t drwl t sddato t dpgc t daak t hadro t dwro t adrckh t adrck t adrckl 00667-018 read cycle write cycle f i g u re 9. sy nch r on ous r e ad /writ e b us m a s t er
ad14060/ad14060l rev. b | page 12 of 48 sy nchronous read/ w ritebus sl a v e u s e t h e s e sp e c if ic a t ions for b u s maste r ac c e ss to a sl a v e s i o p re g i ste r s or in te r n a l me mor y in m u l t i p ro c e ss or me mor y sp ac e. t h e b u s mas t er m u s t m e et t h es e b u s sla v e t i mi n g r e q u ir e m e n ts. table 11. s p eci f ications 5 v 3.3 v parameter m i n m a x m i n m a x unit timing requirements: t sadri addres s , sw setup before clkin 15.5 + dt/2 15.5 + dt/2 ns t hadr i addres s , sw hold before clkin 4.5 + dt/2 4.5 + dt/2 ns t srw l i rd / wr low setup before clkin 1 9.5 + 5 dt/16 9.5 + 5 dt/16 ns t hr wli rd / wr low hold after clkin ?3.5 ? 5 dt/16 +8 + 7 dt/16 ?3.25 ? 5 dt/16 +8 + 7 dt/16 ns t rw h p i rd / wr pulse high 3 3 n s t sdat w h data setup before wr high 5 . 5 5 . 5 n s t hdatw h data hold after wr high 1 . 5 1 . 5 n s switching ch aracteristics: t sddat o data delay after clkin 20 + 5 dt/16 20.25 + 5 dt/16 ns t d a ttr data disable after clkin 2 0 ? dt/8 8 ? dt/8 0 ? dt/8 8 ? dt/8 ns t dackad ack delay after ad d r ess, sw 3 1 0 1 0 n s t ackt r ack disable after clkin 3 ?1 ? dt /8 +7 ? dt /8 ?1 ? dt /8 +7 ? dt /8 ns 1 t srw l i (m i n ) = 9.5 + 5 d t /16 wh en t h e m u lt i p roces s or m e m o ry spa c e wa i t st a t e (m msw s bi t i n wait r e gi st er ) i s di s a bled; wh en m m s w s i s en a b le d, t srw l i (m i n ) = 4 + dt/8. 2 se e t h e sect i o n for t h e ca lcu l a t i o n of h o ld t i m e s gi ven ca pa ci t i ve a n d dc loa d s . syst em ho ld ti m e ca lcula t i o n exa m p le 3 t dac k ad i s t rue on ly i f t h e a d dre s s a n d sw i n put s h a ve set u p t i m e s (bef ore cl kin ) grea t er t h a n 10.5 + d t /8 a n d le ss t h a n 18.5 + 3 d t /4. i f t h e a ddr es s a n d sw input s have set u p t i m e s grea t er t h a n 19 + 3 d t /4, t h e n ack i s va li d 15 + d t /4 (m a x ) a f t e r clkin . a sla ve t h a t see s a n a d dre s s wi t h a n m fi e l d m a t ch respon d s with ack regardless of t h e st a t e o f mm s w s or st robe s. a sla ve t h r ee- st a t es ac k every cyc l e wi t h t ac ktr . cl k i n a ddre s s sw ac k da t a (out) wr data (in) t sadri t hadri t hrwli t dattr t hrwli t sdatwh t hdatwh t srwli t rwhpi t rwhpi t dackad t sddato t acktr t srwli read access write access 00667-019 rd f i g u re 10. sy nch r o n ous r e ad/ w ri te b us sl ave
ad14060/ad14060l rev. b | page 13 of 48 multiprocessor bus request and host bus request use these specifications for passing of the bus mastership among multiprocessing adsp-2106xs ( br x) or a host processor ( hbr , hbg ). table 12. specifications 5 v 3.3 v parameter min max min max unit timing requirements: t hbgrcsv hbg low to rd / wr / cs valid 1 19.5 + 5 dt/4 19.5 + 5 dt/4 ns t shbri hbr setup before clkin 2 20 + 3 dt/4 20 + 3 dt/4 ns t hhbri hbr hold before clkin 2 13.5 + 3 dt/4 13.5 + 3 dt/4 ns t shbgi hbg setup before clkin 13 + dt/2 13 + dt/2 ns t hhbgi hbg hold before clkin high 5.5 + dt/2 5.5 + dt/2 ns t sbri br x, cpa setup before clkin 3 13 + dt/2 13 + dt/2 ns t hbri br x, cpa hold before clkin high 5.5 + dt/2 5.5 + dt/2 ns t srpbai rpba setup before clkin 21 + 3 dt/4 21 + 3 dt/4 ns t hrpbai rpba hold before clkin 11.5 + 3 dt/4 11.5 + 3 dt/4 ns switching characteristics: t dhbgo hbg delay after clkin 8 ? dt/8 8 ? dt/8 ns t hhbgo hbg hold after clkin ?2 ? dt/8 ?2 ? dt/8 ns t dbro br x delay after clkin 8 ? dt/8 8 ? dt/8 ns t hbro br x hold after clkin ?2 ? dt/8 ?2 ? dt/8 ns t dcpao cpa low delay after clkin 9 ? dt/8 9.5 ? dt/8 ns t trcpa cpa disable after clkin C2 ? dt/8 +5.5 ? dt/8 ?2 ? dt/8 +5.5 ? dt/8 ns t drdycs redy (o/d) or (a/d) low from cs and hbr low 4 9.5 12 ns t trdyhg redy (o/d) disable or redy (a/d) high from hbg 4 40 + 27 dt/16 40 + 27 dt/16 ns t ardytr redy (a/d) disable from cs or hbr high 4 11 11 ns 1 for first asynchro nous access after hbr and cs asserted, addr 31C0 must be a non-mms value 1/2 t ck before rd or wr goes low, or by t hbgrcsv after hbg goes low. this is easily accomplished by driving an upper address signal high when hbg is asserted. 2 required only for recogn ition in the current cycle. 3 cpa assertion must meet the setup to clkin; de-asser tion does not need to meet the setup to clkin. 4 (o/d) = open drain; (a/d) = active drive.
ad14060/ad14060l rev. b | page 14 of 48 clkin hbr hb g (o u t ) brx (o u t ) hb g ( in) br x ( i n ) hbr re d y ( o /d ) rd wr cs cs hbg ( o ut ) rp b a t hhbgo t dhbgo cp a ( out ) (o/d) cpa ( i n ) ( o / d) t hhbgi t ardytr re d y ( a /d ) o/d = open drain, a/d = active drive h b g is delayed by n clock cycles when wait states or bus lock are in effect. t shbri t hhbri t shbgi t drdycs t hbgrcsv t trdyhg t dbro t hbro t dcpao t trcpa t srpbai t hrpbai 00667-020 t hbri t sbri f i gur e 1 1 . mul t i p r o c e sso r bus request a n d h o st bus req u est
ad14060/ad14060l rev. b | page 15 of 48 asy n chronous read/writehost t o ad1 4060/ad140 60l u s e t h es e s p ecif ica t ion s f o r asy n c h r o n o us h o st p r o c es s o r access t o a n ad1406 0/ad14060l, a f t e r th e h o s t has as s e r t ed cs an d hb r (lo w ). af t e r hb g is r e t u r n e d b y th e ad140 60/ad14060l, t h e h o s t ca n dr i v e th e rd a nd wr p i n s t o acces s t h e ad14060/ad14060l s in t e r n al me mor y or iop re g i ste r s . hb r a nd hb g a r e a s s u m e d lo w f o r th i s ti m i n g . table 13. s p eci f ications 5 v 3.3 v parameter m i n m a x m i n m a x unit read c y cle timing requirements: t sadrdl addres s setup/ cs low before rd low 1 0 . 5 0 . 5 n s t hadrdh ad d r ess hold / cs hold low after rd 0 . 5 0 . 5 n s t wr wh rd / wr high width 6 6 n s t drdhrdy rd high delay after redy (o/d) dis a ble 0 0 n s t drdhrdy rd high delay after redy (a/d ) disable 0 0 n s switching ch aracteristics: t sdat rdy data valid before redy disable from low 1.5 1.5 ns t drdy rdl redy (o/ d ) or ( a / d ) low del a y after rd low 1 1 1 3 . 5 n s t rdy p rd redy (o/d) or ( a /d) low pulse width for read 45 + dt 45 + dt ns t hdar wh data disable after rd high 1 . 5 9 1 . 5 9 . 5 n s write c y cle timing requirements: t scsw rl cs low setup before wr low 0 . 5 0 . 5 n s t hcsw rh cs low hold after wr high 0 . 5 0 . 5 n s t sadw rh address setup before wr high 5 . 5 5 . 5 n s t hadwr h ad d r ess hold after wr high 2 . 5 2 . 5 n s t wwr l wr low width 7 7 n s t wr wh rd / wr high width 6 6 n s t dw rh rdy wr high del a y after redy (o/ d ) or (a/ d ) dis a bl e 0 . 5 0 . 5 n s t sdat w h data setup before wr high 5 . 5 5 . 5 n s t hdatw h data hold after wr high 1 . 5 1 . 5 n s switching ch aracteristics: t drdy wrl redy (o/ d ) or ( a / d ) low del a y after wr / cs low 1 1 1 3 . 5 n s t rdy p w r redy (o/d) or ( a /d) low pulse width for write 15 15 ns t srdy ck redy (o/ d ) or ( a / d ) dis a bl e to clkin 0 + 7 dt/16 8 + 7 dt/16 0 + 7 dt/16 8 + 7 dt/16 ns 1 no t re quired , i f rd a n d a d dre s s a r e va li d t hbg r c s v af ter hbg go es low. f o r first acce ss after hbr is ass e rted , addr 31 C0 m u st be a n o n - mms va lue 1/2 t cl k be for e rd or wr goes l o w or by t hbg r c s v af ter hbg goe s low . th i s i s ea si ly a ccom p li sh ed by dri v i n g a n upper a d dre s s si g n a l h i gh wh en hbg i s a s sert e d . f o r a ddr es s bi t s t o be dri v en during asynchrono us ho st a cces s e s , se e t h e adsp - 2 1 06x s h ar c users man u al . cl k i n redy (o/d) o/d = open drain, a/d = active drive redy (a/d) t srdyck 00667-021 f i gure 12. s y nch r onous red y t i ming
ad14060/ad14060l rev. b | page 16 of 48 redy (o/d) rd address/cs read cycle write cycle data (out) redy (a/d) o/d = open drain, a/d = active drive redy (o/d) wr t sadwrh t hadwrh t hcswrh t scswrl data (in) address redy (a/d) cs t sadrdl t hadrdh t sdatrdy t rdyprd t wrwh t wwrl t drdyrdl t drdhrdy t hdarwh t wrwh t hdatwh t sdatwh t drdywrl t rdypwr t dwrhrdy 00667-022 f i gure 13. a s ynchrono us r e ad /write h os t to a d s p - 2 1 06x
ad14060/ad14060l rev. b | page 17 of 48 three-st a t e timing bus master, bus sl a v e, hbr , sb t s th e s e sp e c if ic a t io n s sh o w h o w t h e m e m o r y in te r f ace is dis a b l e d (s t o ps dr i v i n g) o r ena b le d (r es u m es dr ivi n g) r e l a t i v e t o clki n a nd t h e sbt s p i n. this timing is a p p l icab le to b u s mas t er tran si tio n c y c l es (b t c ) and h o s t t r a n si tio n c y c l es (ht c ) as we l l as th e sbt s pi n . table 14. s p eci f ications 5 v 3.3 v parameter m i n m a x m i n m a x unit timing requirements: t st sck sbts setup before clkin 12.5 + dt/2 12.5 + dt/2 ns t ht sck sbts hold before clkin 5.5 + dt/2 5.5 + dt/2 ns switching ch aracteristics: t miena ad d r ess/select enable after clk i n ?1.5 ? dt /8 ?1.25 ? dt /8 ns t miens strobes enab le after clkin 1 ?1.5 ? dt /8 ?1.5 ? dt /8 ns t mien hg hbg enable after clkin ?1.5 ? dt /8 ?1.5 ? dt /8 ns t mitr a ad d r ess/select disabl e after clkin 1 ? dt /4 1.25 ? dt /4 ns t mitr s strobes disa ble after clkin 1 2.5 ? dt/4 2.5 ? dt/4 ns t mitr hg hbg disable after cl kin 3 ? dt/4 3 ? dt/4 ns t dat e n data enable aft e r clkin 2 9 + 5 dt/16 9 + 5 dt/16 ns t d a ttr data disable after clkin 2 0 ? dt/8 8 ? dt/8 0 ? dt/8 8 ? dt/8 ns t acken ack enable afte r clkin 2 7.5 + dt/4 7.5 + dt/4 ns t ackt r ack disable after clkin 2 ?1 ? dt /8 +7 ? dt /8 ?1 ? dt /8 +7 ? dt /8 ns t adcen adrclk enable after clkin ?2 ? dt/8 ?2 ? dt/8 ns t adct r adrclk disable after clkin 9 ? dt /4 9 ? dt /4 ns t mtr h bg memory interface disable befor e hbg low 3 ?1 + dt /8 ?1 + dt /8 ns t menh bg memory interface enable after hbg high 3 18.5 + dt 18.5 + dt ns 1 st robe s = rd , wr , sw , pag e, d mag . 2 in a d di t i on t o bus m a s t e r t r a n si t i on cycle s , t h e s e speci f i c a t i o n s a lso a pply t o bus m a s t e r a n d bu s sla ve syn c h r on ou s r e a d /wri t e. 3 mem o ry i n t e rfa c e = a d dre ss, rd , wr , ms x, sw , hbg , page, d mag x, bms (i n e p r o m bo ot m o d e ). cl ki n sb t s ac k memo r y i n t e r f ace hbg memory interface adrclk data memory interface t stsck t daten t acken t acktr t dattr t m e n hbg t htsck t miena , t miens , t mienhg t adcen t adctr t mtrhbg t mitra , t mitrs , t mitrhg 00667-023 = address, rd, wr, msx, sw, hbg, page, dmagx. bms (in eprom boot mode) f i g u re 14. th r e e - st ate ti m i ng
ad14060/ad14060l rev. b | page 18 of 48 dma handshake these specifications describe the three dma handshake modes. in all three modes, dmar is used to initiate transfers. for handshake mode, dmag controls the latching or enabling of data externally. for external handshake mode, the data transfer is controlled by the addr 31-0 , rd , wr , sw , page, ms 3-0 , ack, and dmag signals. for paced master mode, the data transfer is controlled by addr 31-0 , rd , wr , ms 3-0 , and ack (not dmag ). for paced master mode, the memory readbus master, memory writebus master, and synchronous read/writebus master timing specifications for addr 31-0 , rd , wr , ms 3-0 , sw , page, data 47-0 , and ack also apply. table 15. specifications 5 v 3.3 v parameter min max min max unit timing requirements: t sdrlc dmar x low setup before clkin 1 5 5 ns t sdrhc dmar x high setup before clkin 1 5 5 ns t wdr dmar x width low (nonsynchronous) 6 6 ns t sdatdgl data setup after dmag x low 2 9 + 5 dt/8 9 + 5 dt/8 ns t hdatidg data hold after dmag x high 2 2 ns t datdrh data valid after dmag x high 2 15.5 + 7 dt/8 15.5 + 7 dt/8 ns t dmarll dmag x low edge to low edge 23 + 7 dt/8 23 + 7 dt/8 ns t dmarh dmag x width high 6 6 ns switching characteristics: t ddgl dmag x low delay after clkin 9 + dt/4 16 + dt/4 9 + dt/4 16 + dt/4 ns t wdgh dmag x high width 6 + 3 dt/8 6 + 3 dt/8 ns t wdgl dmag x low width 12 + 5 dt/8 12 + 5 dt/8 ns t hdgc dmag x high delay after clkin ?2 ? dt/8 +7 ? dt/8 ?2 ? dt/8 +7 ? dt/8 ns t vdatdgh data valid before dmag x high 3 7.5 + 9 dt/16 7.5 + 9 dt/16 ns t datrdgh data disable after dmag x high 4 ?1 +7.5 ?1 +7.5 ns t dgwrl wr low before dmag x low ?0.5 +2.5 ?0.75 +2.5 ns t dgwrh dmag x low before wr high 9.5 + 5 dt/8 + w 9.5 + 5 dt/8 + w ns t dgwrr wr high before dmag x high 0.5 + dt/16 3.5 + dt/16 0.5 + dt/16 3.5 + dt/16 ns t dgrdl rd low before dmag x low ?0.25 +2.5 0 2.5 ns t drdgh rd low before dmag x high 11 + 9 dt/16 + w 11 + 9 dt/16 + w ns t dgrdr rd high before dmag x high 0 3.5 0 3.5 ns t dgwr dmag x high to wr , rd , dmag x low 4.5 + 3 dt/8 + hi 4.5 + 3 dt/8 + hi ns t dadgh address/select valid to dmag x high 16 + dt 16 + dt ns t ddgha address/select hold after dmag x high ?1.5 ?1.5 ns w = number of wait states specified in wait register t ck . hi = t ck , if an address hold cycle or bus idle cycle occurs, as specified in wait register; otherwise, hi = 0. 1 required only for recogn ition in the current cycle. 2 t sdatdgl is the data setup requirement, if dmar x is not being used to hold off comp letion of a write. otherwise, if dmar x low holds off completion of the write, the data can be driven t datdrh after dmar x is brought high. 3 t vdatdgh is valid, if dmar x is not being used to hold off completion of a read. if dmar x is used to prolong the read, then t vdatdgh = 7.5 + 9 dt/16 + ( n t ck ), where n equals the number of extra cycles that the access is prolonged. 4 see the section for the calculation of hold times given capacitive and dc loads. system hold time calculation example
ad14060/ad14060l rev. b | page 19 of 48 clkin dmar x data (from adsp-2106x to external drive) data (from external drive to adsp-2106x) rd dmagx 1 memory read ? bus master, memory write ? bus master, and synchronous read/write ? bus master. timing specifications for addr 31 ? 0 , rd, wr, sw, ms 3-0 , and ack also apply here. (external device to external memory) (external memory to external device) address ms x , sw transfers between external device and external memory 1 (external handshake mode) transfers between adsp-2106x internal memory and external device t sdrlc t dmarll t wdr t sdrhc t wdgl t dmarh t hdgc t ddgl t wdgh t vdatdgh t datrdgh t hdatidg t dgwrr t dgwrl t dgrdl t dgrdr t ddgha t datdrh t sdatdgl t dgwrh t drdgh t dadgh 00667-024 wr f i gure 15. dma handshak e t i ming
ad14060/ad14060l rev. b | page 20 of 48 table 16. 1 clk speed operation 5 v 3.3 v parameter min max min max unit receive timing requirements: t sldcl data setup before lclk low 3.5 3 ns t hldcl data hold after lclk low 3 3 ns t lclkiw lclk period (1 operation) t ck t ck ns t lclkrwl lclk width low 6 6 ns t lclkrwh lclk width high 5 5 ns switching characteristics: t dlahc lack high delay after clkin high 18 + dt/2 29.5 + dt/2 18 + dt/2 30 + dt/2 ns t dlalc lack low delay after lclk high 1 ?3 +13.5 ?3 +13.5 ns t endlk lack enable from clkin 5 + dt/2 5 + dt/2 ns t tdlk lack disable from clkin 21 + dt/2 21 + dt/2 ns transmit timing requirements: t slach lack setup before lclk high 18 20 ns t hlach lack hold after lclk high ?7 ?7 ns switching characteristics: t dlclk lclk delay after clkin (1 operation) 16.5 17.5 ns t dldch data delay after lclk high 3.5 3 ns t hldch data hold after lclk high ?3 ?3 ns t lclktwl lclk width low (t ck /2) ? 2 (t ck /2) + 2 (t ck /2) ? 1 (t ck /2) + 2.25 ns t lclktwh lclk width high (t ck /2) ? 2 (t ck /2) + 2 (t ck /2) ? 2.25 (t ck /2) + 1 ns t dlaclk lclk low delay after lack high (t ck /2) + 8.5 (3 t ck /2) + 17.5 (t ck /2) + 8 (3 t ck /2) + 18.25 ns t endlk ldat, lclk enable after clkin 5 + dt/2 5 + dt/2 ns t tdlk ldat, lclk disable after clkin 21 + dt/2 21 + dt/2 ns link port service request interrupts: 1 and 2 speed operations timing requirements: t slck lack/lclk setup before clkin low 2 10 10 ns t hlck lack/lclk hold after clkin low 2 2.5 2.5 ns 1 lack goes low with t dlalc relative to the rising edge of lclk after the first nibble is received. lack does not go low, if the receivers link buffer is not about to fill. 2 required only for interrupt re cognition in the current cycle.
ad14060/ad14060l rev. b | page 21 of 48 table 17. 2 clk speed operation 5 v 3.3 v parameter min max min max unit receive timing requirements: t sldcl data setup before lclk low 2.75 2.25 ns t hldcl data hold after lclk low 2.25 2.25 ns t lclkiw lclk period (2 operation) t ck /2 t ck /2 ns t lclkrwl lclk width low 4.6 5.25 ns t lclkrwh lclk width high 4.25 4.5 ns switching characteristics: t dlahc lack high delay after clkin high 18 + dt/2 31.5 + dt/2 18 + dt/2 30.5 + dt/2 ns t dlalc lack low delay after lclk high 1 6 17.8 6 19 ns transmit timing requirements: t slach lack setup before lclk high 20.25 19 ns t hlach lack hold after lclk high ?6.5 ?6.5 ns switching characteristics: t dlclk lclk delay after clkin 9 9 ns t dldch data delay after lclk high 3.25 2.75 ns t hldch data hold after lclk high ?2 ?2 ns t lclktwl lclk width low (t ck /4) ? 1 (t ck /4) + 1.5 (t ck /4) ? 0.75 (t ck /4) + 1.5 ns t lclktwh lclk width high (t ck /4) ? 1.5 (t ck /4) + 1 (t ck /4) ? 1.5 (t ck /4) + 1 ns t dlaclk lclk low delay after lack high (t ck /4) + 9 (3 t cl /4) + 17 (t ck /4) + 9 (3 t cl /4) + 17 ns 1 lack goes low with t dlalc relative to the rising edge of lclk after the first nibble is received. lack does not go low, if the receivers link buffer is not about to fill.
ad14060/ad14060l rev. b | page 22 of 48 clkin lclk ldat(3:0) lack lclk 1x or lclk 2x clkin ldat(3:0) lack (in) lclk 1x or lclk 2x ldat(3:0) lack (out) the t slach requirement applies to the rising edge of lclk only for the first nibble transmitted. clkin link port enable or three-state takes effect 2 cycles after a write to a link port control register. clkin lclk lack last nibble transmitted first nibble transmitted lclk inactive (high) out in lack goes low only after the second nibble is received. t dlclk t hldcl t endlk t slck t dlahc t dlalc t lclktwh t hldch t lclktwl t dldch t sldcl t tdlk t hlck t lclkrwh t lclkrwl t slach t hlach t dlaclk t lclkiw link port interrupt setup time link port enable/three-state delay from instruction receive transmit 00667-025 f i g u re 16. link p o r t s
ad14060/ad14060l rev. b | page 23 of 48 table 18. serial ports 5 v 3.3 v parameter min max min max unit external clock timing requirements: t sfse tfs/rfs setup before tclk/rclk 1 4 4 ns t hfse tfs/rfs hold after tclk/rclk 1 , 2 4.5 4.5 ns t sdre receive data setup before rclk 1 2 2 ns t hdre receive data hold after rclk 1 4.5 4.5 ns t sclkw tclk/rclk width 9.5 9.5 ns t sclk tclk/rclk period t ck t ck ns internal clock timing requirements: t sfsi tfs setup before tclk 1 ; rfs setup before rclk 1 9.5 9.5 ns t hfsi tfs/rfs hold after tclk/rclk 1 , 2 1 1 ns t sdri receive data setup before rclk 1 4.5 4.5 ns t hdri receive data hold after rclk 1 3 3 ns external or internal clock switching characteristics: t dfse rfs delay after rclk (internally generated rfs) 3 14.5 14.5 ns t hfse rfs hold after rclk (internally generated rfs) 3 2.5 2.5 ns external clock switching characteristics: t dfse tfs delay after tclk (internally generated tfs) 3 14.5 14.5 ns t hfse tfs hold after tclk (internally generated tfs) 3 3 3 ns t ddte transmit data delay after tclk 3 17.5 17.5 ns t hdte transmit data hold after tclk 3 5 5 ns internal clock switching characteristics: t dfsi tfs delay after tclk (internally generated tfs) 3 5 5 ns t hfsi tfs hold after tclk (internally generated tfs) 3 ?1.5 ?1.5 ns t ddti transmit data delay after tclk 3 7.5 7.5 ns t hdti transmit data hold after tclk 3 ?0.5 ?0.5 ns t sclkiw tclk/rclk width (sclk/2) ? 2 (sclk/2) + 2 (sclk/2) ? 2.5 (sclk/2) + 2.5 ns enable and three-state switching characteristics: t ddten data enable from external tclk 3 3.5 4 ns t ddtte data disable from external tclk 3 12 12 ns t ddtin data enable from internal tclk 3 ?0.5 ?0.5 ns t ddtti data disable from internal tclk 3 3 3 ns t dclk tclk/rclk delay from clkin 23.5 + 3 dt/8 23.5 + 3 dt/8 ns t dptr sport disable after clkin 18.5 18.5 ns gated sclk with external tfs (mesh multiprocessing) timing requirements: t stfsck tfs setup before clkin 5.5 5.5 ns t htfsck tfs hold after clkin (tck/2) + 0.5 (tck/2) + 0.5 ns
ad14060/ad14060l rev. b | page 24 of 48 5 v 3.3 v parameter m i n m a x m i n m a x unit external late f r ame sync switching ch aracteristics: t ddt lf se data delay from late exte rnal tfs or external rfs with m c e = 1, mfd = 0 4 1 4 . 1 1 4 . 3 n s t ddt enf s data enable from late fs or mc e = 1, mfd = 0 4 3 . 0 3 . 5 n s to de te rmine whe the r co mmunicatio n is pos s i ble be twee n two d e vice s at clo c k s p e e d n , the f o ll owing s p ecif ications mus t be co n f i r m e d: 1) fra m e syn c d e la y a n d fra m e syn c s e t u p a n d h o l d , 2 ) da t a de la y a n d da t a s e t u p a n d h o l d , a n d 3) scl k wi dt h . 1 r e f e ren c e d t o sa m p le edg e . 2 r f s h o ld a f t e r r c k wh en mc e = 1, mf d = 0 i s 0.5 n s m i n i m u m from dri v e ed ge. tf s h o ld a f t e r t c k for la t e ext e rn a l tfs i s 0.5 n s m i n i m um from dri v e e d g e . 3 reference d to driv e e d ge. 4 m c e = 1, tfs en a b l e a n d tf s va li d fol l o w t ddtl f se a n d t ddten f s . drive sample drive tclk tfs dt drive sample drive first bit second bit dt rclk rfs first bit second bit late external tfs external rfs with mce = 1, mfd = 0 t sfse/i t hfse/i 1 t hfse/i 1 t ddtlfse t ddtenfs t hdte/i t ddte/i t sfse/i t ddte/i t hdte/i t ddtenfs t d d t l f s e 00667-026 1 rfs hold after rck when mce = 1, mfd = 0 is 0.5ns minimum from drive edge. tfs hold after tck for late external tfs is 0.5ns minimum from drive edge. f i g u re 17. e x ter n a l l a te f r am e sy nc
ad14060/ad14060l rev. b | page 25 of 48 dt dt drive edge drive edge drive edge tclk/rclk tclk (int) tclk/rclk tclk (ext) rclk rfs dr drive edge sample edge rclk rfs dr drive edge sample edge sample edge note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. tclk tfs dt tclk tfs dt clkin sport enable and three-state latency is two cycles sport disable delay from instruction low to high only tclk (int) rclk (int) tclk, rclk tfs, rfs, dt clkin tfs (ext) note: applies only to gated serial clock mode with external tfs, as used in the serial port system i/o for mesh multiprocessing. note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. data receive ? internal clock data receive ? external clock data transmit ? internal clock data transmit ? external clock t sclkiw t sclkw t dfse t dfse t hfsi t hfse t hdri t hdre t sfsi t sfse t sdri t sdre t hfse t hfse 00667-027 t dfsi t dfse t hfsi t hfse t sfsi t dptr t stfsck t htfsck t sfse t hfsi t ddtin t dclk t ddtti t hfse drive edge sample edge drive edge t sclkiw t sclkw t ddti t hdti t ddten t ddtte t ddte t hdte drive edge f i gure 18. s e ri al p o r t s
ad14060/ad14060l rev. b | page 26 of 48 table 19. j t ag test access port and e m ul ation 5 v 3.3 v parameter m i n m a x m i n m a x unit timing requirements: t tc k tck perio d t ck t ck n s t st ap tdi, tms set u p before tck high 5 ns t htap tdi, tms hold af ter tck high 6 6 ns t ssy s system inputs setup before tck low 1 7 8 n s t hsys system inputs h o ld after tck low 1 1 8 . 5 1 9 n s t tr s t w trst pulse width 4 t ck 4 t ck n s switching ch aracteristics: t dt do tdo delay from tck low 13.5 13.5 ns t dsy s system outputs delay after tck low 2 2 0 2 0 n s 1 sy st em in put s = d a ta 47- 0 , a ddr 31- 0 , rd , wr , ack, sbts , sw , hbr , hbg , cs , d mar 1 , d mar 2 , br 6- 1 , rpba, irq 2- 0 , flag2-0, dr0, dr1, tclk0, tc lk1, rclk0, rclk1, tfs0, tfs1, rfs0, rfs1, l x dat 3- 0 , lxclk, l x ack, eboot, l b oot, bms , clk i n, re se t . 2 sy st em out p ut s = d a ta 47- 0 , a ddr 31- 0 , ms 3- 0 , rd , wr , ack, pag e , adrclk, sw , hbg , re dy, d mag1 , d mag2 , br 6- 1 , cp a , flag 2- 0 , timexp, dt0, dt1, tclk0, t c lk1, r c lk0, rclk1, tfs0, tfs1, rfs0, rfs1, lxdat 3- 0 , lxclk, lxack, bms . tc k tms tdi tdo syst em in p u ts syst em o ut p u t s t tck t dsys t stap t dtdo t ssys t hsys t htap 00667-028 f i gur e 1 9 . ieee 1 149 9 . 1 j t a g t e st a c c e ss p o r t
ad14060/ad14060l rev. b | page 27 of 48 absolute maximum ratings table 20. p a r a m e t e r s r a t i n g s supply voltage (5 v) ?0.3 v to +7 v supply voltage (3.3 v) ?0.3 v to +4.6 v input voltage ?0.5 v to v dd + 0.5 v output voltage swing ?0.5 v to v dd + 0.5 v load capacitance 200 pf junction tempe r ature under bias 130c storage temperature range ?65c to +150c l e a d 2 8 0 c s t r e s s es g r e a t e r t h a n t h os e lis t e d a b o v e ma y c a us e p e r m a n e n t da ma g e t o t h e de v i ce . th es e a r e s t r e s s ra t i n g s on l y ; f u n c t i o n al op e r a t i o n of t h e d e v i c e a t t h e s e or an y ot he r c o nd it i o n s g r e a te r t h a n t h os e i n di c a t e d in t h e o p er a t io nal s e c t io n s o f t h is sp e c if ic a t ion is n o t i m plie d . e x p o sur e t o a b s o lu t e maxi m u m r a t i n g condi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vic e rel i a b i l it y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad14060/ad14060l rev. b | page 28 of 48 pin conf iguration and fu nction descriptions 78 154 15 5 23 1 232 30 8 1 77 a d 140 60/a d 1406 0l top view 00667-043 f i g u re 20. 3 08-l e a d c qfp pin conf ig u r at i o n
ad14060/ad14060l rev. b | page 29 of 48 table 21. pin numbers and mnemonics pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic pin no. mnemonic 1 wr 45 gnd 89 addr13 133 irq b0 177 lc4dat2 221 gnd 265 gnd 2 rd 46 rfsd1 90 addr12 134 irq b1 178 lc4dat3 222 la3ack 266 data24 3 gnd 47 rclkd1 91 addr11 135 irq b2 179 gnd 223 la3clk 267 data25 4 csa 48 drd1 92 gnd 136 gnd 180 lc3ack 224 la3dat0 268 data26 5 csb 49 tfsd1 93 addr10 137 irq c0 181 lc3clk 225 la3dat1 269 data27 6 csc 50 tclkd1 94 addr9 138 irq c1 182 lc3dat0 226 la3dat2 270 v dd 7 csd 51 dtd1 95 addr8 139 irq c2 183 lc3dat1 227 la3dat3 271 data28 8 gnd 52 v dd 96 v dd 140 irq d0 184 lc3dat2 228 v dd 272 data29 9 hbg 53 hbr 97 addr7 141 irq d1 185 lc3dat3 229 la1ack 273 data30 10 redy 54 dmar 1 98 addr6 142 irq d2 186 v dd 230 la1clk 274 data31 11 adrclk 55 dmar 2 99 addr5 143 v dd 187 lc1ack 231 la1dat0 275 gnd 12 v dd 56 sbts 100 gnd 144 eboota 188 lc1clk 232 la1dat1 276 data32 13 rfs0 57 bmsa 101 addr4 145 lboota 189 lc1dat0 233 la1dat2 277 data33 14 rclk0 58 bmsbcd 102 addr3 146 ebootbcd 190 lc1dat1 234 la1dat3 278 data34 15 dr0 59 sw 103 addr2 147 lbootbcd 191 lc1dat2 235 gnd 279 data35 16 tfs0 60 gnd 104 v dd 148 gnd 192 lc1dat3 236 data0 280 v dd 17 tclk0 61 ms 0 105 addr1 149 reset 193 gnd 237 data1 281 data36 18 dt0 62 ms 1 106 addr0 150 rpba 194 lb4ack 238 data2 282 data37 19 gnd 63 ms 2 107 flaga0 151 gnd 195 lb4clk 239 data3 283 data38 20 cpaa 64 ms 3 108 gnd 152 ld4ack 196 lb4dat0 240 v dd 284 data39 21 cpab 65 v dd 109 flaga2 153 ld4clk 197 lb4dat1 241 data4 285 gnd 22 cpac 66 addr31 110 flagb0 154 ld4dat0 198 lb4dat2 242 data5 286 data40 23 cpad 67 addr30 111 flagb2 155 ld4dat1 199 lb4dat3 243 data6 287 data41 24 v dd 68 addr29 112 flagc0 156 ld4dat2 200 v dd 244 data7 288 clkin 25 rfsa1 69 gnd 113 flagc2 157 ld4dat3 201 lb3ack 245 gnd 289 gnd 26 rclka1 70 addr28 114 flagd0 158 v dd 202 lb3clk 246 data8 290 data42 27 dra1 71 addr27 115 flagd2 159 ld3ack 203 lb3dat0 247 data9 291 data43 28 tfsa1 72 addr26 116 v dd 160 ld3clk 204 lb3dat1 248 data10 292 v dd 29 tclka1 73 v dd 117 flag1 161 ld3dat0 205 lb3dat2 249 data11 293 data44 30 dta1 74 addr25 118 emu 162 ld3dat1 206 lb3dat3 250 v dd 294 data45 31 gnd 75 addr24 119 timexpa 163 ld3dat2 207 gnd 251 data12 295 data46 32 rfsb1 76 addr23 120 timexpb 164 ld3dat3 208 lb1ack 252 data13 296 data47 33 rclkb1 77 addr22 121 timexpc 165 gnd 209 lb1clk 253 data14 297 gnd 34 drb1 78 addr21 122 timexpd 166 ld1ack 210 lb1dat0 254 data15 298 br 1 35 tfsb1 79 addr20 123 gnd 167 ld1clk 211 lb1dat1 255 gnd 299 br 2 36 tclkb1 80 v dd 124 tdo 168 ld1dat0 212 lb1dat2 256 data16 300 br 3 37 dtb1 81 addr19 125 trst 169 ld1dat1 213 lb1dat3 257 data17 301 br 4 38 v dd 82 addr18 126 tdi 170 ld1dat2 214 v dd 258 data18 302 br 5 39 rfsc1 83 addr17 127 tms 171 ld1dat3 215 la4ack 259 data19 303 br 6 40 rclkc1 84 gnd 128 tck 172 v dd 216 la4clk 260 v dd 304 page 41 drc1 85 addr16 129 v dd 173 lc4ack 217 la4dat0 261 data20 305 v dd 42 tfsc1 86 addr15 130 irq a0 174 lc4clk 218 la4dat1 262 data21 306 dmag 1 43 tclkc1 8 addr14 131 irq a1 175 lc4dat0 219 la4dat2 263 data22 307 dmag 2 44 dtc1 88 v dd 132 irq a2 176 lc4dat1 220 la4dat3 264 data23 308 ack
ad14060/ad14060l rev. b | page 30 of 48 pin function descriptions ad14060/ad14060l pin function descriptions are listed in table 22. inputs identified as synchronous (s) must meet timing requirements with respect to clkin (or with respect to tck for tms, tdi). inputs identified as asynchronous (a) can be asserted asynchronously to clkin (or to tck for trst ). unused inputs should be tied or pulled to v dd or gnd, except for addr 31-0 , data 47-0 , flag 2-0 , sw , and inputs that have internal pull-up or pull-down resistors (cpa, ack, dtx, drx, tclkx, rclkx, lxdat 3-0 , lxclk, lxack, tms, and tdi) these pins can be left floating. these pins have a logic-level hold circuit that prevents the input from floating internally. table 22. pin function descriptions pin type 1 function addr 31-0 i/o/t external bus address (common to all sharcs). the ad14060/ad14060l outputs addresse s for external memory and peripherals on these pins. in a multiprocessor system, the bus master outputs addresses for read/writes on the internal memory or iop registers of slave adsp- 2106xs. the ad14060/ad14060l inputs addresses when a host processor or multiprocessing bus master is reading or wr iting the internal memory or iop registers of internal adsp-21060s. data 47-0 i/o/t external bus data (common to all sharcs). the ad14060/ ad14060l inputs and outputs da ta and instructions on these pins. 32-bit single-precision floati ng-point data and 32-bit fixed-point da ta is transferred over bits 47C16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47C48 of the bus. 16-bit short word data is transferred over bits 31C16 of the bus. in prom boot mode, 8-bit data is transfe rred over bits 23C16. pull-up resistors on unused data pins are not necessary. ms 3-0 o/t memory select lines (common to all sharcs). these lines are asserted (low) as chip selects for the corresponding banks of external memory. memory ba nk size must be defined in the in dividual adsp-21060s system control registers (syscon). the ms 3-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring, the ms 3-0 lines are inactive. they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. ms 0 can be used with the page signal to implement a bank of dram memory (bank 0). in a multiprocessing system, the ms 3-0 lines are output by the bus master. rd i/o/t memory read strobe (common to all sharcs). this pin is asserted (low ) when the ad14060/ad14060l reads from external devices or when the internal memory of internal adsp-2106xs is being accessed. external devices (including other adsp-2106xs) must assert rd to read from the ad14060/ad14060l s internal memory. in a multiprocessing system, rd is output by the bus master and is input by all other adsp-2106xs. wr i/o/t memory write strobe (common to all sharcs). this pi n is asserted (low) when the ad14060/ad14060l writes to external devices or when the internal memory of internal adsp-2106xs is being accessed. external devices (including other adsp-2106xs) must assert wr to write to the ad14060/ ad14060ls internal memory. in a multiprocessing system, wr is output by the bus master and is input by all other adsp-2106xs. page o/t dram page boundary. the ad14060/ad16060l asserts this pin to signal that an external dram page boundary has been crossed. dram page size must be defined in th e individual adsp-21060s memory control register (wait). dram can be implemented only in external memory ban k 0. the page signal can be activated only for bank 0 accesses. in a multiprocessing system , page is output by the bus master. adrclk o/t clock output reference (common to all sharcs). in a multiprocessing syst em, adrclk is output by the bus master. sw i/o/t synchronous write select (common to all sharcs). this signal is used to interface the ad14060/ad14060l to synchronous memory devices (including other adsp-2106xs). the ad14060/ad14060l asserts sw (low) to provide an early indication of an impending write cycle, which can be aborted, if wr is not later asserted (for example, in a conditional write inst ruction). in a multiprocessing system, sw is output by the bus master and is input by all other adsp-2106xs to determine if the multiprocess or memory access is a read or write. sw is asserted at the same time as the address output. a host processor using synchronou s writes must assert this pin when writing to the ad14060/ad14060l. ack i/o/s memory acknowledge (common to all sharcs). external devices can de-assert ac k (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other peripherals to hold off comple- tion of an external memory access. the ad14060/ad14060l de-asserts ack, as an output, to add wait states to a synchronous access of its internal memory. in a multiprocessin g system, a slave adsp-2106x de-asserts the bus masters ack input to add wait state(s) to an access of its internal memory. the bus master has a keeper latch on its ack pin that maintains the input at the level to which it was last driven.
ad14060/ad14060l rev. b | page 31 of 48 pin type 1 function sbts i/s suspend bus three-state (common to all sharcs). external devices can assert sbts (low) to place the external bus address, data, selects, and strobes in a high impedan ce state for the following cycle. if the ad14060/ad14060l attempts to access external memory while sbts is asserted, the processor halts and the memory access does not complete until sbts is de-asserted. sbts should be used only to recover from host processor/ad14060/ad14060l deadlock, or used with a dram controller. hbr i/a host bus request (common to all sharcs). must be asse rted by a host processor to request control of the ad14060/ad14060ls external bus. when hbr is asserted in a multiprocessing system, the adsp-2106x that is bus master relinquishes the bus and asserts hbg . to relinquish the bus, the adsp-2106x places the address, data, select, and strobe lines in a high impedance state. hbr has priority over all adsp-2106x bus requests ( br 6-1 ) in a multiprocessing system. hbg i/o host bus grant (common to a ll sharcs). acknowledges an hbr bus request, indicating that the host processor can take control of the external bus. hbg is asserted (held low) by the ad14060/ad14060l until hbr is released. in a multiprocessing system, hbg is output by the adsp-2106x bus master and is monitored by all others. csa i/a chip select. asserted by host processor to select sharc_a. csb i/a chip select. asserted by ho st processor to select sharc_b. csc i/a chip select. asserted by ho st processor to select sharc_c. csd i/a chip select. asserted by ho st processor to select sharc_d. redy (o/d) o host bus acknowledge (common to all sharcs). the ad 14060/ad14060l de-asserts redy (l ow) to add wait states to an asynchronous access of its internal memory or iop registers by a host. open-drain output (o/d) by default; can be programmed in adredy bit of syscon register of individual adsp-21060s to be active drive (a/d). redy is output only if the cs and hbr inputs are asserted. br 6-1 i/o/s multiprocessing bus requests (common to all sharcs). us ed by multiprocessing adsp-2106xs to arbitrate for bus mastership. an adsp-2106x drives only its own br x line (corresponding to the value of its id2-0 inputs) and monitors all others. in a multiprocessor system with less than six adsp-2106xs, the unused br x pins should be pulled high; br 4-1 must not be pulled high or low, because they are outputs. rpba i/s rotating priority bus arbitration sele ct (common to all sharcs). when rpba is high, rotating priority for multi- processor bus arbitration is selected. when rpba is low, fixed priority is selected. this signal is a system configuration selection that must be set to the same va lue on every adsp-2106x. if the value of rpba is changed during system operation, it must be changed in the same clkin cycle on every adsp-2106x. cpa y (o/d) i/o core priority access (y = sharc_a, b, c, d). asserting its cpa pin allows the core processor of an adsp-2106x bus slave to interrupt background dma transfer s and gain access to the external bus. cpa is an open-drain output that is connected to all adsp-2106xs in the syst em, if this function is required. the cpa pin of each internal adsp-21060 is brought out individually. the cpa pin has an internal 5 k? pull-up resistor. if core access priority is not required in a system, the cpa pin should be left unconnected. dt0 o/t data transmit (common serial po rts 0 to all sharcs, tdm). the dt pin has a 50 k? internal pull-up resistor. dr0 i data receive (common serial port s 0 to all sharcs, tdm). the dr pin has a 50 k? internal pull-up resistor. tclk0 i/o transmit clock (common serial ports 0 to all sharcs, tdm). the tclk pin has a 50 k? internal pull-up resistor. rclk0 i/o receive clock (common serial ports 0 to all sharcs, tdm). the rclk pin has a 50 k? internal pull-up resistor. tfs0 i/o transmit frame sync (common serial ports 0 to all sharcs, tdm). rfs0 i/o receive frame sync (common se rial ports 0 to all sharcs, tdm). dty1 o/t data transmit (serial port 1 individual from sharc_a, sharc_b, sharc_c, sharc_d). the dt pin has a 50 k? internal pull-up resistor. dry1 i data receive (serial port 1 individual from sharc_a, sharc_b, sharc_c, sharc_d). the dr pin has a 50 k? internal pull-up resistor. tclky1 i/o transmit clock (serial port 1 individual from sharc_a , sharc_b, sharc_c, sharc_d). the tclk pin has a 50 k? internal pull-up resistor. rclky1 i/o receive clock (serial port 1 individual from sharc_a , sharc_b, sharc_c, sharc_d). the rclk pin has a 50 k? internal pull-up resistor. tfsy1 i/o transmit frame sync (serial port 1 indi vidual from sharc_a, sharc_b, sharc_c, sharc_d). rfsy1 i/o receive frame sync (serial port 1 indi vidual from sharc_a, sharc_b, sharc_c, sharc_d). flagy0 i/o/a flag pins (flag0 individual from sharc_a, sharc_b, sharc_ c, sharc_d). each pin is configured via control bits as either an input or an output. as an input, it can be tested as a conditio n. as an output, it ca n be used to signal external peripherals.
ad14060/ad14060l rev. b | page 32 of 48 pin type 1 function flag1 i/o/a flag pins (flag1 common to all sharcs). this pin is configured via contro l bits internal to individual adsp-21060s as either an input or an output. as an input, it can be tested as a conditio n. as an output, it ca n be used to signal external peripherals. flagy2 i/o/a flag pins (flag2 individual from sharc_a, sharc_b, sharc_ c, sharc_d). each pin is configured via control bits as either an input or an output. as an input, it can be tested as a conditio n. as an output, it ca n be used to signal external peripherals. irq y2-0 i/a interrupt request lines (individual irq 2-0 from y = sharc_a, sharc_b, sharc_c, sharc_d). can be either edge- triggered or level-sensitive. dmar1 i/a dma request 1 (dma channel 7). commo n to sharc_a, sharc_b, sharc_c, sharc_d. dmar2 i/a dma request 2 (dma channel 8). commo n to sharc_a, sharc_b, sharc_c, sharc_d. dmag1 o/t dma grant 1 (dma channel 7). common to sharc_a, sharc_b, sharc_c, sharc_d. dmag2 o/t dma grant 2 (dma channel 8). common to sharc_a, sharc_b, sharc_c, sharc_d. lyxclk i/o link port clock (y = sharc_a, b, c, d; x = link ports 1, 3, 4) 2 . each lyxclk pin has a 50 k? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register of the adsp-20160. lyxdat3-0 i/o link port data (y = sharc_a, b, c, d; x = link ports 1, 3, 4) 2 . each lyxdat pin has a 50 k? internal pull-down resistor that is enabled or disabled by the lpdrd bit of the lcom register of the adsp-21060. lyxack i/o link port acknowledge (y = sharc_a, b, c, d; x = link ports 1, 3, 4) 2 . each lyxack pin has a 50 k? internal pull- down resistor that is enabled or disabled by the lpdrd bit of the lcom register of the adsp-21060. eboota i eprom boot select (sharc_a). when eboota is high, sharc_a is configured for booting from an 8-bit eprom. when eboota is low, the lboota and bmsa inputs determine booting mode for sharc_a. see the following table. this signal is a system configuration selection that should be hardwired. lboota i link boot. when lboota is high, sharc_a is configured for link port booting. when lboota is low, sharc_a is configured for host processor booting or no booting. see th e following table. this signal is a system configuration selection that should be hardwired. bmsa i/o/t 3 boot memory select. when this pin is an output, it is used as chip select for boot eprom devices (when eboota = 1, lboota = 0). in a multiprocessor system, bms is output by the bus master. as an input, when low, this pin indicates that no booting is to occur and that sharc_a is to begin executing instructions from external memory. see the following table. this input is a system configuration selection that should be hardwired. ebootbcd i eprom boot select (common to sharc_b, sharc_c, shar c_d). when ebootbcd is high, sharc_b, c, and d are configured for booting from an 8-bit eprom. when ebootbcd is low, the lbootbcd and bmsbcd inputs determine booting mode for sharc_b, c, and d. see the follo wing table. this signal is a system configuration selection that should be hardwired. lbootbcd i link boot (common to sharc_b, sharc_c, sharc_d). when lbootbcd is high, sharc_b, c, and d are configured for link port booting. when lbootbcd is low, sharc_b, c, and d are configured for host processor booting or no booting. see the following table. this signal is a syst em configuration selection th at should be hardwired. bmsbcd i/o/t 3 boot memory select. when this pin is an output, it is used as chip select for boot eprom devices (when ebootbcd = 1, lbootbcd = 0). in a multiprocessor system, bms is output by the bus master. as an input, when low, this pin indicates that no booting is to occur an d that sharc_b, c, and d are to begin executing instructions from external memory. see table below. this input is a system co nfiguration selection that should be hardwired. eboot lboot bms booting mode 1 0 output eprom (connect bms to eprom chip select). 0 0 1 (input) host processor. 0 1 1 (input) link port. 0 0 0 (input) no booting. processor executes from external memory. 0 1 0 (input) reserved. 1 1 x (input) reserved. timexpy o timer expired (individual timexp from y = sharc_a, sharc_b, sharc_c, sharc_d). asserted for four cycles when the timer is enabled and tcount decrements to 0. clkin i clock in (common to all sharcs). ex ternal clock input to the ad14060/ad14060l. the instruction cycle rate is equal to clkin. clkin cannot be halted, changed, or operated below the minimum specified frequency. reset i/a module reset (common to all sharcs ). resets the ad14060/ad14060l to a kn own state. this input must be asserted (low) at power-up. tck i test clock (jtag) (common to all sharcs). prov ides an asynchronous cloc k for jtag boundary scan. tms i/s test mode select (jtag) (common to all sharcs). used to control the test state machine. tms has a 20 k? internal pull-up resistor.
ad14060/ad14060l rev. b | page 33 of 48 pin type 1 function tdi i/s test data input (jtag). provides serial data for the boundary scan logic chain starting at sharc_a. tdi has a 20 k? internal pull-up resistor. tdo o test data output (jtag). serial scan outp ut of the boundary scan chain path, from sharc_d. trst i/a test reset (jtag) (common to all shar cs). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the ad14060/ad14060l. trst has a 20 k? internal pull-up resistor. emu (o/d) o emulation status (common to all sharcs ). must be connected to the adsp- 2106x ez-ice target board connector only. v dd p power supply. nominally 5.0 v dc for 5 v devi ces or 3.3 v dc for 3.3 v devices (26 pins). gnd g power supply return (28 pins). flag3 is connected internally, common to sharc_a, b, c, and d. id pins are hardwired interna lly as shown in figure 1. 1 i = input; p = power supply; (a/d) = active drive; o = output; s = synchronous; (o/d) = open drain; g = ground; a = asynchrono us; t = three-state, when sbts is asserted, or when the ad14060/ad14060l is a bus slave. 2 link ports 0, 2, and 5 are connected internally, as described in the li section. nk port i/o 3 three-statable only in eprom boot mode (when bms is an output).
ad14060/ad14060l rev. b | page 34 of 48 detailed description architectural features adsp-21060 core the ad14060/ad14060l is based on the powerful adsp-21060 (sharc) dsp chip. the adsp-21060 sharc combines a high performance floating-point dsp core with integrated, on-chip system features, including a 4-mbit sram memory, host processor interface, dma controller, serial ports, and both link port and parallel bus connectivity for glueless dsp multiprocessing (see figure 21). it is fabricated in a high speed, low power cmos process, and has a 25 ns instruction cycle time. the arithmetic/logic unit (alu), multiplier, and shifter all perform single-cycle instructions, and the three units are arranged in parallel, maximizing computational throughput. the sharc features an enhanced harvard architecture, in which the data memory (dm) bus transfers data and the program memory (pm) bus transfers both instructions and data. an on-chip instruction cache selectively caches only those instructions whose fetches conflict with the pm bus data accesses. this combines with the separate program and data memory buses to enable 3-bus operation for fetching an instruction and two operands, all in a single cycle. the sharc also contains a general-purpose data register file, which is a 10-port, 32-register (16 primary, 16 secondary) file. each sharcs core also implements two data address generators (dags), implementing circular data buffers in hardware. the dags contain sufficient registers to allow the creation of up to 32 circular buffers. the 48-bit instruction word accommodates a variety of parallel operations for concise programming. for example, the adsp-21060 can conditionally execute a multiply, an add, a subtract, and a branch, all in a single instruction. the sharcs contain 4 mbits of on-chip sram each, organized as two blocks of 2 mbits, which can be configured for different combinations of code and data storage. the memory can be configured as a maximum of 128k words of 32-bit data, 256k words of 16-bit data, 80k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 4 mbits. a 16-bit floating-point storage format is supported, which effectively doubles the amount of data that can be stored on- chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. each memory block is dual-ported for single-cycle, independent access by the core processor and i/o processor or dma controller. the dual-ported memory and separate on-chip buses allow two data transfers from the core and one from the i/o, all in a single cycle. shared memory multiprocessing the ad14060/ad14060l takes advantage of the powerful multiprocessing features built into the sharc. the sharcs are connected to maximize the performance of this cluster-of- four architecture, and still allow for off-module expansion. the ad14060/ad14060l in itself is a complete shared memory multiprocessing system, as shown in figure 22. the unified address space of the sharcs allows direct interprocessor accesses of each sharcs internal memory. in other words, each sharc can directly access the internal memory and iop registers of each of the other sharcs by simply reading or writing to the appropriate address in multiprocessor memory space (see figure 23)this is called a direct read or direct write. bus arbitration is accomplished with the on-sharc arbitration logic. each sharc has a unique id, and drives the bus-request (br) line corresponding to its id, while monitoring all others. br 1 to br 4 are used within the ad14060/ad14060l, while br 5 and br 6 can be used for expansion. all bus requests ( br 1 to br 6) are included in the module i/o. two different priority schemes, fixed and rotating, are available to resolve competing bus requests. the rpba pin selects which scheme is used. when rpba is high, rotating priority bus arbitration is selected; when rpba is low, fixed priority is selected. bus mastership is passed from one sharc to another during a bus transition cycle. a bus transition cycle occurs only when the current bus master de-asserts its br line and one of the slave sharcs asserts its br line. the bus master can, therefore, retain bus mastership by keeping its br line asserted. when the bus master de-asserts its br line and no other br line is asserted, then the master does not lose any bus cycles. when more than one sharc asserts its br line, the sharc with the highest priority request becomes bus master on the following cycle. each sharc observes all the br lines, and, therefore, tracks when a bus transition cycle has occurred, and which processor has become the new bus master. master processor changeover incurs only one cycle of overhead. table 23 shows an example of a bus transition sequence. table 23. rotating priority arbitration example hardware processor ids cycle id1 id2 id3 id 4 id5 id6 priority 1 m 1 2 br 3 4 5 initial priority assignments 2 4 5 br m-br 1 2 3 3 4 5 br m 1 2 3 4 5 br m 1 2 3 4 br 5 1 br 2 3 4 5 m final priority assignments 1C5 = assigned priority. m = bus mastership (in that cycle). br = requesting bus mastership with br x.
ad14060/ad14060l rev. b | page 35 of 48 data addr data addr block 1 data addr data addr two independent dual-ported blocks processor port i/o port block 0 i/o processor timer instruction cache 32 x 48-bit jtag test and emulation dual-ported sram external port host port addr bus mux multiprocessor interface data bus mux pm address bus dm address bus pm data bus dm data bus 24 core processor dag1 8 x 4 x 32 dag2 8 x 4 x 24 32 program sequencer multiplier barrel shifter alu data register file 16 x 40-bit 48 40/32 7 32 48 4 6 6 36 bus connect (px) iod 48 ioa 17 serial ports (2) link ports (6) dma controller iop registers (memory mapped) control, status, and data buffers 00667-003 f i g u re 21. a d s p -2 1 0 6 0 pr o c es s o r bl oc k d i ag r a m (core of a d 10 46 0) cl ki n r eset rp ba cp a bootselect a bootselect bcd dmar1, 2 dmag1, 2 sport0 flag1 jtag 1 clock s h arc_ d links 1, 3, and 4; ir q 2?0 ; flags 2 and 0; timexp, sport1 sharc_c links 1, 3, and 4; ir q 2? 0 ; flags 2 and 0; timexp, sport1 rd wr ack ms 3-0 page sbts sw adrclk cs hbr hbg redy br 1?6 data 47?0 addr 31?0 sharc_a links 1, 3, and 4; ir q 2?0 ; flags 2 and 0; timexp, sport1 sharc_b links 1, 3, and 4; ir q 2? 0 ; flags 2 and 0; timexp, sport1 a d 1 4060/a d 14060l (q u a d pr o c esso r c l u st er ) system expansion 00667-005 f i gure 22. co mpl e te sh ared me m o r y multip r o cessing s y stem
ad14060/ad14060l rev. b | page 36 of 48 iop registers normal word addressing 0x0000 0000 0x0002 0000 0x0004 0000 0x0008 0000 0x0010 0000 0x0018 0000 0x0020 0000 0x0028 0000 0x0030 0000 0x0038 0000 0x003f ffff short word addressing internal memory space of sharc_b id = 010 internal memory space of sharc_a id = 001 internal memory space of sharc_c id = 011 internal memory space of sharc_d id = 100 internal memory space of adsp-2106x id = 101 internal memory space of adsp-2106x id = 110 broadcast write to all adsp-2106xs normal word addressing: 32-bit data words 48-bit instruction words short word addressing: 16-bit data words ms 0 0x0040 0000 0xffff ffff multiprocessor memory space bank 0 bank 1 bank 2 dram (optional) bank 3 nonbanked ms 1 ms 2 ms 3 bank size is selected by msize bit field of syscon register external memory space internal memory space (individual sharcs) internal to ad14060 external to ad14060 00667-004 f i gur e 2 3 . ad14 060 / a d1 40 60 l m e mo r y ma p bus lo ck in g is p o ssi b le , a l lo wing indivisib l e r e a d - m o d if y - wr i t e s e q u e n ces fo r s e ma ph o r es. i n e i t h er t h e f i xe d o r r o t a t i n g p r io r i ty s c h e m e , i t is als o p o s s i b l e t o limi t the n u m b er o f c y c l es tha t t h e mas t er ca n us e t o co n t rol th e b u s. the ad14060/ ad14060l p r o v ides the o p tio n o f usin g th e co r e p r io r i ty acces s (cp a ) m o de o f th e s h arc. u s in g th e cp a signal allo ws ext e r n al b u s acc e s s es b y t h e co re p r o c es s o r o f a s l a v e s h ar c t o t a ke pr i o r i t y ove r ongoi n g dm a t r ans f e r s . a l s o , e a ch sh a r c ca n b r o a dca s t w r i t e to a l l o t h e r s h arc s sim u l t a n e o usly , allo w i n g th e im p l e m en t a ti o n o f r e f l ecti v e se m a p h o r e s . the b u s mas t er ca n comm u n ic a t e w i t h s l a v e sh ar cs b y wr i t i n g m e s s a g e s t o t h eir i n t e r n al i o p r e g i s t ers. the ms r g 0 t o ms r g 7 r e g i s t ers a r e g e n e ral - p u r p os e r e g i s t ers t h a t c a n b e us e d for c o n v e n ie n t me ss age p a ss ing , s e ma p h ore s , and re s o u r c e s h a r in g am o n g t h e sh arcs. f o r m e s s a g e p a s s i n g, t h e mast er co mm uni c a t es wi t h a sl a v e b y wr i t i n g an d / o r r e adin g an y o f t h e eig h t m e s s a g e reg i s t ers o n t h e sla v e . f o r v e c t o r in t e r r u p ts, t h e maste r c a n is su e a ve c t or i n te r r u p t to a s l a v e b y wr i t ing t h e addr es s o f a n in t e r r u p t s e r v ice r o u t ine t o t h e s l a v e s vir p t r e g i st er . this c a us es a n im m e d i a t e h i g h p r io r i ty in t e r r u p t o n t h e sla v e , w h ich, w h en s e r v ic e d , c a u s es i t t o b r an ch t o t h e sp e c if ie d se r v i c e r o u t in e . off-modul e memor y and peripher als interf a c e the ad14060/ad14060l s exter n al p o r t p r o v ides th e in t e r f ace to of f - mo d u l e me mor y an d p e r i phe r a l s ( s e e f i g u re 2 4 ) . t h i s p o r t co n s is ts o f t h e com p let e ex t e r n al p o r t b u s o f t h e s h ar c, bu s e d i n c o m m on a m ong t h e f o u r sh a r c s . the 4-g i g a w o r d o f f-m o d u le addr es s s p ace is i n cl ude d in t h e ads p -14060 s u n if ied addr es s sp ace . a ddr es sing o f ext e r n al me mor y d e v i c e s i s f a c i l i t a te d by e a ch sh a r c i n te r n a l ly d e c o d i ng t h e h i g h - o rd e r a d d r e s s l i ne s to ge ne r a te me mor y - ba nk s e le c t sig n als. s e p a ra t e con t r o l lin e s a r e als o g e n e ra t e d f o r sim p lif i ed addres sin g o f p a g e -m o d e d r am. th e ad14060 / ad14060l als o s u p p o r ts p r og ra mma b l e m e m o r y wa i t s t a t es a n d ext e rn al m e m o r y a c kn o w le d g e co n t r o ls t o allo w i n t e rfa c i n g to dr am an d p e r i ph er a l s wi t h va r i a b le acce ss, h o ld , and dis a b l e t i me r e quir em e n ts.
ad14060/ad14060l rev. b | page 37 of 48 addr 31? 0 data 47? 0 cpa br 2? 6 br 1 bms control ad14060/ ad14060l 1x clock reset addr data host processor interface (optional) ack cs global memory and peripherals (optional) oe we addr data cs addr data boot eprom (optional) rd wr ms 3? 0 sbts sw adrclk cs hbr hbg redy ack rpba page id 2? 0 serials links discretes 101 clkin addr 31? 0 data 47? 0 cpa br 1? 4, 6 br 5 control adsp-2106x #5 (optional) rpba clkin 3 5 5 id 2? 0 110 addr 31? 0 data 47? 0 cpa br 1? 5 br 6 control adsp-2106x #6 (optional) reset rpba clkin 3 5 reset reset 00667-007 f i gure 24. o p tion al s y stem in te r c onne c t ions
ad14060/ad14060l rev. b | page 38 of 48 link port i/ o e a c h in di vid u al s h ar c fe a t ur e s six 4-b i t lin k p o r t s tha t f a c i l i t a te sh a r c - to - s h a r c c o mm u n i c a t i o n and e x te r n a l i / o in t e r f acing. e a ch lin k p o r t can be co nf igur e d f o r ei th er 1 o r 2 o p era t ion, al lo win g e a ch t o t r a n sfer ei t h er fo ur o r eig h t b i t s pe r c y c l e . the lin k p o r t s c a n o p er a t e inde p e nden t ly and sim u l t ane o usly , w i t h a m a x i m u m b a n d w i d t h of 4 0 m b y t e s / s e a ch , or a tot a l of 240 mb yt es/s p e r s h ar c. the ad14060/ad14060l o p timizes the lin k p o r t co nn ec tion s i n te r n a l ly , a n d br i n g s a tot a l of 1 2 of t h e l i n k p o r t s of f - mo d u l e fo r us er -def in e d sys t em conne c t io n s . i n ter n al l y , e a ch s h ar c h a s a co nn ecti o n t o th e o t h e r th r e e s h ar c s wi th a d e d i ca t e d lin k p o r t i n ter f a c e. th us, e a ch sh arc ca n dir e c t ly in ter f ace w i t h it s ne are s t an d ne x t - n e a re s t ne i g h b or . t h e re m a i n i n g t h re e l i n k p o r t s f r om e a ch sh a r c ar e brou g h t out i n d e p e nd e n t l y f r o m eac h s h ar c. a maxim u m o f 480 mb yt es/s lin k p o r t ba ndwid th is t h en a v a i lab l e o f f o f th e ad14060 /ad14060l. the lin k p o r t conn ec t i o n s a r e sh o w n in f i gur e 25. s h arc_ a s har c_ b s h arc_ d s har c_ c 1 3 4 1 3 4 55 2 2 0 0 55 2 2 1 3 4 1 3 4 0 0 00667-006 f i gure 25. link p o r t c o nn ec tions l i n k p o r t 4 , t h e b o ot - l i n k p o r t , i s brou g h t of f i n d e p e nd e n t l y f r om e a ch sh a r c . i n d i v i d u a l b o ot i n g i s t h e n a l l o we d, or cha i n e d l i n k -p or t b o o t in g is p o ssi b le, as des c r i b e d in t h e m u lt ipro c e ss or l i n k - p or t b o ot i n g s e c t i o n . l i nk p o r t da ta is p a c k e d in t o 32 -b i t o r 48-b i t wo r d s, a n d can b e d i re c t ly re a d by t h e sh a r c c o re pro c e s s o r or dm a t r ans f e r re d to on - s h a rc me mor y . e a ch lin k p o r t has i t s own doub le- b uf fer e d in pu t an d o u t p ut r e gi s t er s. cloc k / a c kn o w le d g e h a n d s haki n g co n t r o ls li nk po r t tra n sfers. t r a n sfers a r e p r og ra mma b l e as e i t h er tra n smi t o r re c e ive. serial port s the s h ar c s e r i al p o r t s p r o v ide a n i n exp e n s i v e in ter f ace t o a wid e va r i ety o f dig i t a l an d mixe d-sig n a l p e r i ph er a l d e vices. e a c h s h ar c has tw o s e r i a l p o r t s. th e ad140 60/ad14060l p r o v ides dir e c t acces s t o s e r i al p o r t 1 o f eac h s h ar c. s e r i al p o r t 0 is b u s e d i n co m m on to e a ch s h arc, and b r o u g h t o f f- mo d u l e . the s e r i al p o r t s ca n op era t e a t t h e f u l l clo c k r a te o f t h e m o d u le , p r o v idin g e a ch wi t h a maxim u m da t a ra t e o f 40 mb i t /s. i ndep e n d en t t r an smi t and r e ceive f u n c t i on s p r o v ide m o r e f l exi b le co mm u n ica t io n s . s e r i a l p o r t da t a ca n b e a u t o ma t i ca l l y t r a n sfer r e d to a nd f r o m o n - s h a rc m e m o r y v i a d m a, an d e a ch o f t h e s e r i a l p o r t s o f fers t i m e -division- m u l t i p lexe d (tdm) mu l t i c h a n n e l m o d e . the s e r i a l p o r t s ca n op er a t e wi t h li t t le-e n d ian or b i g-e ndi a n tra n smis sio n for m a t s, wi th w o rd len g th s s e le c t a b le f r o m 3 b i ts to 3 2 b i t s . t h e y of fe r s e l e c t abl e s y nc h r on i z a t i o n an d t r ans m i t m o de s as wel l a s o p t i o n a l - la w o r a - l a w com p a nding. s e r i a l p o r t clo c ks an d f r a m e sy n c s can b e i n t e r n a l ly o r ext e r n a l ly ge ne r a te d. progr a m bo o t i n g the ad14060/ad14060l s u p p o r ts a u t o ma tic do wnlo ading o f pro g r a ms f o l l o w i n g p o we r - up or a s o f t w a re re s e t . t h e sh a r c of f e r s t h e f o l l ow i n g opt i on s f o r pro g r a m b o ot i n g : ? fr o m a n 8 - b i t e p r o m ? fr o m a h o s t pr o c e s s o r ? thr o ug h t h e li n k p o r t s ? no b o o t i n n o - b o o t m o d e , t h e sh arc st a r ts exe c u t in g in st r u c t io n s f r o m a ddr es s 0 x 0040 0004 in ext e r n al m e m o r y . th e bo ot m o de is s e le c t e d b y t h e s t a t e o f t h e fol l o w in g sig n als: bms , e b o o t , a nd lb o o t . on the ad1406 0/ad14060l, s h ar c_ a s bo ot m o de is s e p a - ra t e ly con t r o l l e d , w h i l e s h arc_b , c, a nd d ar e co n t r o l l e d as a g r o u p . w i th this f l exi b ili t y , th e ad14060/ad1 4060l ca n be c o n f i g u r e d to b o ot u s i n g a n y of t h e f o l l ow i n g me t h o d s . multipro cessor host booting t o bo o t m u l t i p l e ads p -21060 p r o c es s o rs f r o m a h o st, eac h ads p -21060 m u s t ha v e i t s eb o o t , lb o o t , and bms pi ns co nf igur ed f o r h o s t bo o t in g: eb o o t = 0, lb o o t = 0, an d bms = 1. af t e r sys t em p o w e r - u p , eac h ads p -21060 is in t h e idle s t a t e and t h e br x b u s r e q u es t l i n e s a r e de- a s s e r t e d . th e ho st m u st as s e r t t h e hb r in p u t an d bo o t e a c h ads p -21060 b y ass e r t in g i t s cs p i n and do w n lo adin g in st r u c t io n s .
ad14060/ad14060l rev. b | page 39 of 48 multiprocessor eprom booting the following methods boot the multiprocessor system from an eprom: ? sharc_a is booted, which then boots the others. the eboot pin on the sharc_a must be set high for eprom booting. all other adsp-21060s should be configured for host booting (eboot = 0, lboot = 0, and bms = 1), which leaves them in the idle state at startup and allows sharc_a to become bus master and boot itself. only the bms pin of sharc_a is connected to the chip select of the eprom. when sharc_a has finished booting, it can boot the remaining adsp-21060s by writing to their external port dma buffer 0 (epb0) via multiproc- essor memory space. ? all adsp-21060s boot in turn from a single eprom. the bms signals from each adsp-21060 can be wire-ored together to drive the chip select pin of the eprom. each adsp-21060 can boot in turn, according to its priority. when the last one has finished booting, it must inform the others (which can be in the idle state) that program execution can begin. multiprocessor link-port booting booting can also be accomplished from a single source through the link ports. link buffer 4 must always be used for booting. to simultaneously boot all the adsp-21060s, a parallel common connection is available through link port 4 on each of the processors. or, using the daisy-chain connection that exists between the processors link ports, each adsp-21060 can boot the next one in turn. in this case, the link assignment register (lar) must be programmed to configure the internal link ports with link buffer 4. multiprocessor booting from external memory if external memory contains a program after reset, then sharc_a should be set up for no-boot mode. it begins execut- ing from address 0x0040 0004 in external memory. when booting has completed, the other adsp-21060s can be booted by sharc_a, if they are set up for host booting; or they can begin executing out of external memory, if they are set up for no-boot mode. multiprocessor bus arbitration allows this booting to occur in an orderly manner. host processor interface the ad14060/ad14060ls host interface allows easy connec- tion to standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. asynchronous transfers at speeds of up to the full clock rate of the module are sup- ported. the host interface is accessed through the ad14060/ ad14060l external port and is memory-mapped into the unified address space. four channels of dma are available for the host interface; code and data transfers are accomplished with low software overhead. the host processor requests the ad14060/ad14060ls external bus with the host bus request ( hbr ), host bus grant ( hbg ), and ready (redy) signals. the host can directly read and write the internal memory of the sharcs, and can access the dma channel setup and mailbox registers. vector interrupt support is provided for efficient execution of host commands. direct memory access (dma) controller the sharcs on-chip dma control logic allows zero-overhead data transfers without processor intervention. the dma controller operates independently and invisibly to each sharcs processor core, allowing dma operations to occur while the core is simultaneously executing its program instructions. dma transfers can occur between sharc internal memory and either external memory, external peripherals, or a host processor. dma transfers can also occur between the sharcs internal memory and its serial ports or link ports. dma transfers between external memory and external peripheral devices are another option. external bus packing to 16-, 32- or 48-bit words is performed during dma transfers. ten channels of dma are available on the sharcs: two via the link ports, four via the serial ports, and four via the processors external port (for either host processor, other sharcs, memory, or i/o transfers). four additional link port dma channels are shared with serial port 1 and the external port. programs can be downloaded to the sharcs using dma transfers. asynchronous off-module peripherals can control two dma channels using dma request/grant lines ( dmar 1-2, dmag 1-2). other dma features include interrupt generation upon completion of dma transfers and dma chaining for automatic linked dma transfers.
ad14060/ad14060l rev. b | page 40 of 48 applications development tools the ad14060/ad14060l is supported with a complete set of software and hardware development tools, including an in-circuit emulator and development software. analog devices, inc. (adi) uses visualdsp++?, which is an easy-to-use integrated software development and debugging environment (idde) that efficiently manages projects from start to finish from within a single interface. the adsp-21262 ez-kit lite? pr ovides developers with a cost-effective method for initia l evaluation of the adsp-2106x sharc processor architecture for applications via a usb-based pc-hosted tool set. with this ez-kit lite, users can learn about adis adsp-2106x hardware and software development and can quickly prototype applications. the ez-kit lite includes an adsp-2106x processor desktop evaluation board, along with an evaluation suite of the visualdsp++ development and debugging environment with the c/c++ compiler, assembler, and linker. visualdsp++ development and debugging software, along with the usb- based debugger interface, enab les users to perform standard debugging functions (such as read and write memory, read and write registers, load and exec ute executables, set and clear breakpoints, and single-step assembly, c, and c++ source code). the adi cost-effective universal serial bus (usb)-based emulator and high performance (hp) universal serial bus (usb)-based emulator each provide an easy, portable, non- intrusive, target-based debugging solution for adi jtag processors and dsps. these powerful usb-based emulators perform a wide range of emulation functions, including single- step and full speed execution with predefined breakpoints, and viewing and altering of register and memory contents. with the ability to automatically detect and support multiple i/o voltages, the usb and hp usb emulators enable users to communicate with all the adi jtag processors and dsps using either a full speed usb 1.1 or high speed usb 2.0 port on the host pc. applications and data can be easily and rapidly tested and transferred between the emulators and the separately available visualdsp++ development and debugging environ- ment (sold separately). the plug-and-play architecture of the usb allows the host operating system to automatically detect and configure the emulators. the usb can be connected to and disconnected from the host without opening the pc or turning off the power to the pc. a 3-meter cable is included to connect the emulators to the host pc, providing abundant accessibility to hard-to- reach targets. the hp usb-based emulator supports the background telemetry channel (btc), a nonintrusive method for exchang- ing data between the host and target application without affecting the target system's real -time characteristics. nonintru- sive in-circuit emulation is assured by the use of the processors jtag interface. the emulator does not affect target system loading or timing. further details and ordering information are available on the analog.com web site. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hardware tools include sharc pc plug-in cards, multi- processor sharc vme boards, and daughter card modules with multiple sharcs and additional memory. these modules are based on the sharcpac module specification. third-party software tools include an ada compiler, dsp libraries, operating systems, and block diagram design tools. quad-sharc development board the blacktip-mcm, ad14060 development board with software is available from bittware research systems, inc. this board has one ad14060 bitsi interface, and prom and sram expansion options on an isa card. it is supported by bittwares sharc software development package. to contact bittware, call 1-800-848-0436. other package details the ad14060/ad14060l contains 16 on-module 0.018 f bypass capacitors. it is recommended that, in the target system, at least four additional capacitors of 0.018 f value be placed around the module, one near each of the four corners. the top surface (lid) of the ad14060/ad14060l is electrically connected to gnd on the industrial and military grade parts. target board connector for emulator probe the adsp-2106x emulator uses the ieee 1149.1 jtag test access port of the adsp-2106x to monitor and control the target board processor during emulation. the emulator probe requires that the ad14060/ad14060ls clkin (optional), tms, tck, trst , tdi, tdo, emu , and gnd signals be made accessible on the target system via a 14-pin connector (pin strip header) similar to figure 26. the emulator probe plugs directly into this connector for chip-on-board emulation. you must add this connector to your target board design, if you intend to use the adsp-2106x emulator. the length of the traces between the connector and the ad14060/ad14060ls jtag pins should be as short as possible.
ad14060/ad14060l rev. b | page 41 of 48 top view 13 14 11 12 91 0 9 78 56 34 12 emu clkin (optional) tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd 00667-008 table 24. j t ag signals s i g n a l t e r m i n a t i o n tms driven through 22 ? resistor (16 a to 3.2 a dri ver). tck driven at 10 mh z through 22 ? r e sistor (16 a to 3.2 a driver). trst driven by open- drain driver 1 (pulled up by on-ch i p 20 k? resistor) . tdi driven by 16 a to 3.2 a driver. tdo o n e ttl l o ad, no terminatio n. clkin one ttl load, no termination (o ptional signal). emu 4.7 k? pull-up resistor, o n e t t l load ( open-d r ai n output from ad sp-2106x). __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 1 trst is driven low un t i l t h e emulat or prob e is t urn ed on by t h e emu l at or s o f t ware ( a f t er the i n vocation comman d ) . c o n n e c t i ng c l k i n to pi n 4 of t h e e m u l a t or he a d e r i s opt i on a l . the em u l a t o r us es clki n o n l y w h en dir e c t e d to p e r f o r m o p er a t io ns such as st a r t i ng, sto p p i n g , and sin g le -stepp in g m u l t i p le ads p -2106xs in a sy nc hr o n o u s ma nner . i f th es e o p er a t io ns do no t n e e d to o c c u r sy n c hr on o u sly o n t h e m u l t i p le p r o c es s o rs, t i e pin 4 o f t h e e m u l a t o r h e ader t o g r o u n d . f i gur e 2 6 . t a r g e t bo ar d co nnect or for adsp -2 106 x em ula t or (jumpers in place) the 14-pin, 2-ro w p i n- st r i p h e ader is k e ye d a t t h e pi n 3 lo c a - t i o n ; p i n 3 m u s t b e r e m o v e d f r o m t h e h e ader . th e pin s m u s t b e 0.025 in ch s q uar e a nd a t leas t 0. 20 in ch in len g t h . p i n s p ac in g s h o u ld b e 0.1 inc h 0.1 in c h . p i n s t r i p h e aders a r e a v a i la b l e f r om ve nd or s s u ch a s 3 m , m c k e n z i e , a n d s a m t e c . i f s y nch r o n ou s m u lt ipro c e ss or op e r a t i o n s are n e e d e d a n d clki n is co nnec t e d , c l o c k sk e w betw e e n t h e ad14060/ ad14060l and th e clki n p i n o n the em u l a t o r h e ader m u s t be m i n i m a l. i f t h e ske w i s to o l a r g e, s y nc h r onou s op e r a t i o n s m i g h t b e of f by one c y cl e b e t w e e n pro c e s s o r s . f o r s y n c h r onou s m u lt i- p r o c ess o r o p er a t io n, t c k, t m s , clkin, and emu shou l d b e tr e a t e d as cr i t ic al sig n als in t e r m s o f s k e w , an d s h o u ld be la id out a s s h or t a s p o ss ibl e on t h e b o ard. the btm s , btc k , bt r s t , a nd b t d i sig n als a r e p r o v ide d s o tha t t h e t e s t acc e s s p o r t can als o be us ed f o r bo a r d-leve l t e sting . w h en t h e con n e c t o r is n o t b e ing us e d fo r em u l a t io n, pl ace j u m p er s between th e bxxx p i n s a n d t h e o t h e r p i n s , as sh o w n in f i gur e 26. i f yo u a r e n o t g o in g t o us e th e t e s t acces s p o r t f o r boa r d t e sti n g, tie bt r s t t o gnd an d t i e o r p u l l u p b t ck t o v dd . t h e trst p i n m u s t be a s se r t ed a f t e r po w e r - u p ( t h r o u gh bt r s t on t h e c o n n e c t o r ) or hel d l o w f o r prop e r op e r at i o n of th e ad14060 /ad14060l. n o n e o f th e bxxx p i ns (p in s 5, 7, 9, 11) a r e co nn ec ted o n t h e em u l a t o r p r obe . i f t c k, tms, a nd cl kin a r e dr i v in g a la rg e n u m b er o f ads p -2106x s ( m o r e than eig h t) in the sys t em, tr ea t t h em as a clo c k t r e e usin g m u l t i p le dr i v ers to mini mi ze sk e w . (s e e t h e adsp -210 6x u s er s m a n ua l fo r det a i l s) . i f s y nch r o n ou s m u lt ipro c e ss or op e r a t i o n s are n o t ne e d e d (clkin is n o t c o nn e c t e d), us e a p p r o p r i a t e p a ra l l e l t e r m ina t io n o n t c k and tms. n o t e tha t td i, td o , emu , a nd trst are n o t cr i t ical sig n als in t e r m s o f sk e w . the j t a g sig n a l s a r e t e r m ina t e d o n t h e e m u l a t o r p r ob e as lis t e d in t a b l e 2 4 . f i gur e 27 s h o w s jt a g s c an p a t h co nn ec tion s f o r th e m u l t ip ro c e ss or s y ste m .
ad14060/ad14060l rev. b | page 42 of 48 s har c_ a td i t d o tck tms e m u la tor jt a g c o nne c t o r td i tc k tm s emu tr s t td o cl ki n ot h e r j t a g co nt ro l l e r optional sha rc_ b td i t d o tck tms em u trst s harc_c td i t d o tck tms em u trst s harc _ d td i t d o tck tms em u trst j t ag de v i ce (o pt i o n a l ) td i t d o tck tms trst a d s p - 21 06 x #n td i t d o tck tms em u trst em u trst 00667-009 f i g u re 27. jt a g s c a n p a t h conn ectio ns fo r the ad14 060 /ad1 40 60 l system clkin 1 tdi tdo tdi tdo tdi tdo tdi tdo tdi tdo tdi tdo tdi emu tms tck tdo trst clkin 5k ? 1 5k ? 1 open-drain driver or equivalent, that is: emu 00667-010 f i g u re 28. jt a g c l o c k t r ee f o r m u lt ip le a d sp - 2 1 06x sy s t e m s output drive current s f i gur e 29 s h o w s typ i cal i - v c h arac t e r i s t ics f o r th e o u t p u t dr i v ers o f th e ads p -2106x. th e c u r v es r e p r es en t th e c u r r en t d r ive c a p a bi l i t y of t h e output d r ive r s a s a f u nc t i on of output vol t age. 00667-029 source voltage (v) 5 01 2 3 4 s o urce curre nt (ma) 120 60 80 100 20 40 ?40 ?20 0 ?80 ?60 ?140 ?120 ?100 ?160 high level drive (p device) low level drive (n device) f i g u re 29. a d s p -2 1 06x t y pi c a l d r ive current s ( v dd = 5 v ) po wer diss ip a t ion t o tal p o w e r dissi p a tion has two co m p on e n ts, o n e d u e t o in t e r n al cir c ui t r y a n d one d u e to t h e s w i t chi n g o f ext e r n al o u t p ut dr i v ers. i n ter n a l p o w e r d i ssi p a t ion is de p e n d e n t on t h e in st r u c t io n exe c u t io n s e q u e n ce a nd t h e da t a o p er a n ds in volve d . i n ter n a l p o w e r dissi p a t io n is ca lc u l a t e d as fol l o w s: p int = i ddi n v dd the ext e r n al com p on e n t o f t o t a l p o w e r dis s i p a t io n is c a us e d b y t h e s w i t chin g o f o u t p u t p i n s . i t s ma g n i t ude dep e n d s on t h e fol l o w ing : ? n u m b er o f o u t p u t p i ns tha t s w i t c h d u r i n g each c y c l e (o) ? m a xi m u m f r eq ue n c y a t wh i c h th ey ca n sw i t ch (f ) ? lo ad c a p a ci tan c e (c) ? vo l t a g e s w i n g ( v dd ) a nd is ca lc u l a t e d b y p ex t = o c v dd 2 f
ad14060/ad14060l rev. b | page 43 of 48 the lo ad c a p a ci t a nce sh o u ld i n cl ude t h e p r o c ess o r s p a cka g e ca p a c i tan c e (c in ). th e s w i t ching f r e q uen c y in cl udes dr i v i n g t h e lo ad hig h and t h e n b a ck lo w . a ddr ess and d a t a p i n s c a n dr i v e hig h and lo w a t a max i m u m ra te o f 1/(2 t ck ). th e wr i t e s t r o b e ca n s w i t ch ev er y c y c l e a t a f r eq uen c y o f 1/t ck . s e l e c t p i n s s w i t c h at 1 / ( 2 t ck ) , b u t se l e ct s ca n swi t c h o n ea c h c y c l e . ex a m pl e es tima te p ext w i t h t h e fol l owing assu m p t i ons : a s y ste m wi t h one b a n k of e x te r n a l d a t a me m o r y r a m ( 3 2 - bit ) ; f o ur 128k 8 ram c h i p s a r e u s ed , each wi th a lo ad o f 10 pf; ext e r n al da t a mem o r y wr i t es o c c u r e v er y o t h e r c y cle; a ra t e o f 1/(4 t ck ) wi t h 5 0 % o f th e p i n s s w i t c h in g; an d an in str u c t io n c y c l e ra t e is 40 mh z (t ck = 25 n s ) a nd v dd = 5.0 v . the p ext eq u a tio n is calc u l a t e d f o r eac h c l as s o f p i n s tha t can dr i ve, as sh o w n in t a b l e 25.a ty p i ca l p o w e r co nsum p t ion c a n n o w b e ca lc u l a t e d fo r t h es e condi t i on s b y addi n g a ty pica l in t e r n a l p o w e r dissi p a t io n: p to t a l = p ex t + ( i ddi n 2 5.0 v) n o t e t h a t t h e con d i t io ns c a using a w o rst- cas e p ext a r e dif f er en t f r o m th ose ca u s i n g a w o r s t - ca se p int . m a x i m u m p int ca nn o t o c c u r w h i l e 100 % o f t h e o u t p u t p i n s a r e s w i t chi n g f r o m al l 1s to al l 0s. i t is un comm on f o r a n a p p l ica t ion t o ha ve 100% o r ev en 5 0 % of t h e output s s w itch i n g s i m u lt a n e o u sly . test c o n d i t io ns out p ut disabl e tim e ou t p u t p i n s a r e co n s i d e r ed t o b e d i sa b l e d w h en th ey s t o p dr i v i n g, go in to a hig h im p e dance st a t e, and st ar t to de ca y f r o m t h eir o u t p u t hig h o r lo w v o l t a g e. th e t i m e fo r t h e v o l t a g e on t h e b u s t o dec a y b y v is dep e n d en t o n t h e c a p a ci t i v e lo ad , c l , a nd th e loa d curr e n t, i l . this dec a y t i me can be a p p r o x ima t ed b y t h e f o l l ow i n g e q u a t i on : l l decay i v c t ? = the o u t p u t dis a b l e t i m e , t dis , is t h e dif f er en ce b e tw e e n t meas ure d a nd t deca y , a s s h o w n i n f i g u r e 3 0 . t h e t i m e t meas ured is t h e in t e r v al f r o m w h e n t h e r e fer e n c e sig n al s w i t ch e s t o w h en t h e output vo lt ag e d e c a y s v f r om t h e me a s u r e d output h i g h or out p ut l o w vol t age. t deca y is calc u l a t e d wi t h t e st lo ads c l an d i l , a nd wi t h v eq ual t o 0.5 v . out p ut enabl e tim e ou t p u t p i n s a r e co n s i d e r ed t o b e e n a b l e d w h en th ey h a v e ma d e a t r a n si t i on f r o m a hig h i m p e da n c e s t a t e t o w h en t h e y s t a r t dr i v in g. th e ou t p u t ena b le t i m e , t en a , is t h e in t e r v al f r o m w h en a r e fer e n c e sig n al r e ach e s a hig h o r lo w v o l t a g e le v e l t o w h en t h e o u t p ut has r e ach e d a sp e c if ie d hig h o r lo w t r i p p o in t, as sh o w n in t h e o u t p u t en a b le/dis a b le d i ag ra m (f igur e 30). i f m u l t i p le p i n s (s uch as t h e da t a b u s) a r e e n a b le d , t h e m e as ur em e n t val u e i s th a t o f th e f i r s t p i n t o s t a r t d r i v in g. sys t em hol d t i me c a lc ulati o n exam ple t o deter m i n e t h e da t a o u t p u t hold t i me i n a p a r t ic u l a r sys t em, fi r s t c a l c u l a t e t de c a y us i n g th e p r evi o u s eq ua ti o n . ch oose v t o be t h e dif f er en c e betw een t h e ads p -2106x s o u t p u t v o l t a g e an d th e in p u t th r e sh o l d f o r th e d e v i ce r e q u i r i n g t h e h o ld tim e . a typ i cal v is 0. 4 v . c l i s th e t o t a l b u s ca pa ci ta n c e pe r da t a lin e , a nd i l is t h e t o t a l le aka g e o r t h re e-s t a t e c u r r en t p e r da t a l i n e . the h o ld t i m e i s t deca y pl us t h e mini m u m dis a ble t i me (t hdwd fo r t h e wr i t e c y cle). 00667-030 re f e r e nce s i g nal t di s output starts driving v oh (measured) ? ? v v ol (measured) + ? v t measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high-impedance state. test conditions cause this voltage to be approximately 1.5v output stops driving t ena t decay f i g u re 30. o u t p ut e n abl e /d is ab le table 25. p ex t calculations pin type number of pin s % switching c f v dd 2 = p ext address 15 50 55 pf 20 mhz 25 v = 0.206 w mso 1 0 55 pf 20 mhz 25 v = 0.00 w wr 1 C 55 pf 40 mhz 25 v = 0.055 w data 32 50 25 pf 20 mhz 25 v = 0.200 w adrclk 1 C 15 pf 40 mhz 25 v = 0.015 w p ext (5 v) = 0.476 w. p ext (3.3 v) = 0.207 w.
ad14060/ad14060l rev. b | page 44 of 48 c a p a citiv e lo ading o u t p u t dela y s and h o lds a r e b a s e d on st anda rd ca p a ci t i ve lo ad s: 50 pf o n al l p i ns (s ee f i gur e 31 ). th e de l a y an d h o ld sp ecif ic a - tio n s g i v e n sh ou ld be dera ted b y a fac t o r o f 1.5 n s /50 pf f o r lo ads o t h e r than the n o mina l val u e o f 50 pf . f i gur e 33 a n d f i gur e 34 s h o w h o w o u t p u t r i s e time va r i es wi t h c a p a ci t a nce . f i gur e 35 g r a p hical l y s h o w s h o w o u t p u t de l a ys a nd h o lds va r y w i t h loa d ca pa ci ta n c e . (n o t e th a t th i s gra p h o r de ra ti n g d o e s n o t a p pl y t o o u t p u t dis a b l e dela ys; s e e t h e o u t p u t dis a b l e t i m e s e c t i o n . ) t h e g r ap h s i n fi g u r e 3 3 , fi g u r e 3 4 , a n d fi g u r e 3 5 mig h t n o t b e li ne a r o u tside t h e r a n g es sh o w n. i ol i oh 1.5v to output pin 50pf 00667-031 f i g u re 31. equiv a le nt d e v i c e l o ad ing f o r a c m e as u r e m e n t ( i nclud e s a l l f i x t ures ) input or output 1.5v 1.5v 00667-032 f i gure 32. v o ltage r e fer e n c e l e ve ls fo r a c me asurem ent s (ex c ept o u t p ut e n able/d is ab le) 00667-033 load capacitance (pf) 200 0 2 0 4 0 6 0 8 0 100 120 140 160 180 14.7 7.4 ris e and fall time s (ns ) ( 0 .5v ? 4.5v, 10% ? 90%) 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0 1.1 3.7 fall time rise time f i g u re 33. t y pic a l o u t p ut r i s e tim e ( 10% to 9 0 % v dd ) v s . l oad cap a c i t a nc e ( v dd = 5 v ) 00667-034 load capacitance (pf) 200 0 2 0 4 0 6 0 8 0 100 120 140 160 180 2.9 1.6 ris e and fall time s (ns ) ( 0 .8v ? 2.0v) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.6 0 rise time fall time f i g u re 34. t y pic a l o u t p ut r i s e tim e ( 0 .8 v to 2. 0 v ) v s . l oad cap a c i t a nc e ( v dd = 5 v ) 00667-035 load capacitance (pf) 200 25 50 75 100 125 150 175 4.5 outp ut de lay or hold (ns ) 5.0 4.0 3.0 2.0 1.0 ? 0.7 nominal ? 1.0 f i g u re 35. t y pic a l o u t p ut d e l a y or h o ld v s . l oad cap a c i t a nc e a t ma xim u m c a se t e mp e r a t ur e ( v dd = 5 v ) 00667-036 load capacitance (pf) 200 0 2 0 4 0 6 0 8 0 100 120 140 160 180 ris e and fall time s (ns ) ( 10% ? 90%) 18 14 16 12 8 10 6 2 4 0 y = 0.0796x + 1.17 y = 0.0467x + 0.55 rise time fall time f i g u re 36. t y pic a l o u t p ut r i s e tim e ( 10% to 9 0 % v dd ) v s . l oad capa cit a n c e ( v dd = 3. 3 v )
ad14060/ad14060l rev. b | page 45 of 48 00667-037 load capacitance (pf) 200 0 2 0 4 0 6 0 8 0 100 120 140 160 180 ris e and fall time s (ns ) ( 0 .8v ? 2.0v) 9 8 7 5 4 6 3 2 1 0 y = 0.0391x + 0.36 y = 0.0305x + 0.24 rise time fall time f i g u re 37. t y pic a l o u t p ut r i s e tim e ( 0 .8 v to 2. 0 v ) v s . l oad capa cit a n c e ( v dd = 3. 3 v ) 00667-038 load capacitance (pf) 200 25 50 75 100 125 150 175 4.5 outp ut de lay or hold (ns ) 5.0 4.0 ? 0.7 3.0 2.0 1.0 nominal ? 1.0 y = 0.0329x ? 1.65 f i g u re 38. t y pic a l o u t p ut d e l a y or h o ld v s . l oad cap a c i t a nc e a t ma xim u m c a se t e mp e r a t ur e ( v dd = 3. 3 v ) assembl y rec o mmend a t ions socket in formation s t a nda rd s o ck et s a nd ca r r i ers a r e a v a i la b l e fo r t h e ad14060/ad1 4060l, if n eede d . s o ck et p a r t n u m b er i c 53-3084-262 a nd ca r r i er p a r t n u m b er i c c-3 08-1 a r e a v a i la b l e f r o m y a ma ichi e l e c t r onics. trim an d for m the ad14060/ad14060l is s h i p p e d as sh o w n in f i gur e 43 wi t h un t r im m e d an d unfo r m e d le ad s a nd wi t h t h e no n c ond u c t i v e t i e ba r in p l ace . this a v o i ds dis t urb a n c e o f lead s p acin g an d c o pl an ar it y pr i o r to a s s e m b ly . o p t i m a l l y , t h e l e a d s shou l d b e t r imm e d , fo r m e d , a nd s o lder -d i p p e d j u st p r io r to place m en t o n th e boa r d . t r im/fo r m c a n b e ac co m p lishe d w i t h a uni v ers a l t r im/fo r m, a c u s t om er - d esi g n e d t r im/fo r m, o r wi t h t h e analog d e vi ces de velo p e d to oli n g des c r i b e d as fol l o w s. a tr im/f o r m t o ol s p ecif ic t o the ad14060 /ad14060l has b een de velo p e d an d i s a v a i la b l e fo r us e b y a l l p a r t ies a t ti n t r o n i c s in du s t r i e s 2122-a m e tr o cir c le h u n t s v il le , al 3 5801 256-650-0220 co n t a c t p e r s o n : t o m r i c e the p a ck a g e o u t l in e a nd d i m e nsio n s r e su l t in g f r o m t h is t o ol a r e s h own i n f i gur e 39. (a l t er na t i v e l y , t h e p a cka g e c a n b e t r imme d/fo r m e d fo r c a vity -dow n pl ac e m e n t . ) 0.170 (4.318) 2.110 (53.59) 2.210 0.010 (56.134 0.254) 0.016 min 0t o 1 0m i l s 0 to 8 de t a i l a 00667-039 f i g u re 39. p a ckag e and l e ad pr of il e di me nsio ns sho w n i n i n che s a n d ( m il lim e t e r s)
ad14060/ad14060l rev. b | page 46 of 48 pcb l a y o u t guideline s the dra w in g in f i gur e 40 as s u m e s tha t t h e tr im/f o r m t o oling d e scri b e d p r evio u s l y i s used . t h e s e r e co mm en da ti o n s a r e p r o v ide d fo r us er co n v eni e n c e a nd a r e pcb la yo u t guide l i n es on ly , b a s e d on s t an d a rd pr a c t i c e . p c b p a d f o otpr i n t ge o m e t r i e s a nd plac e m en t a r e i l l u st r a te d . 0. 0 1 5 ( 0 . 3 81) 1.9000 (48.26) 4 places 2.060 (52.324) 4 places 2.260 (57.404) 4 places 0.025 (0.635) min this is a pc board component footprint, not the package outline. 0. 0 2 5 ( 0 . 6 35) 0.025 (0.635) min 00667- 040 f i g u re 40. pc bo ard co mpon ent f oot print di me nsio ns sho w n i n i n che s a n d ( m il lim e t e r s) ther m al c h a r act e ris t ics the ad14060/ad14060l is p a c k a g e d in a 308 -lead cera mic q u a d f l a t pa c k (cq f p ) . t h e pa c k a g e i s o p ti mi zed f o r th e r m a l co nd uc t i o n t h ro ug h t h e co r e (b as e o f t h e p a cka g e) do w n t o t h e m o u n tin g s u r f ace . th e ad1406 0/ad14060l is s p ecif ie d f o r a cas e t e m p era t ure (t ca se ). de si gn o f th e m o un tin g s u rfa c e a n d a t tac h m e n t ma ter i al sh o u ld be suc h tha t t ca se i s n o t e x ceeded . ? jc = 0.36c/w thermal cross-section the fol l o w in g da t a , t o g e t h er wi t h t h e det a i l e d m e cha n ic al dra w in gs in f i g u r e 43, al lo ws th e desig n er t o c o n s tr uc t sim p le th e r m a l m o de ls f o r fu r t h e r a n alysi s w i th in ta r g e t ed sys t e m s. the t o p l a yer o f t h e p a cka g e , w h er e t h e die a r e m o u n t e d , is a me t a l v dd la yer . the a p p r o x ima t e m e t a l a r e a co vera g e f r o m t h e m e t a l plan es and r o u t in g l a yers is es t i ma t e d in t a b l e 27. th e l a y e r s are s h ow n i n fi g u re 4 1 . table 26. ther mal con d uctiv ity material thermal conductivity (w/cmc) c e r a m i c 0 . 1 8 k o v a r ? 0 . 1 4 t u n g s t e n 1 . 7 8 t h e r m o p l a s t i c 0 . 0 3 s i l i c o n 1 . 4 5 ta ble 27. met a l covera ge per la yer layer % metal ( 1 mil thick) v dd 88 s i g 2 1 6 s i g 3 1 4 g n d 9 1 s i g 4 1 5 s i g 5 1 3 b a s e 9 5 ceramic layer 28 mils ceramic layer 6 mils ceramic layer 6 mils ceramic layer 10 mils ceramic layer 4 mils ceramic layer 10 mils ceramic layer 10 mils ceramic layer 4 mils ceramic layer 10 mils ceramic layer 4 mils su r f a c e kovar lid 0.015 mils kovar seal ring height = 50 mils silicon die 19 mils thermoplastic thickness 5 mils v dd sig2 sig3 gnd sig4 sig5 base 00667-041 f i gure 41. co -f ired p a ck ag ed pr ofi l e
ad14060/ad14060l rev. b | page 47 of 48 mechanic al char a c teristics lid d e fle c tion analys is table 28. e x ternal pressure re duction press u re deflectio n 12 psi 10.0 mil 15 psi 11.9 mil mech ani c al m o del the fol l o w in g da t a , t o g e t h er wi t h t h e det a i l e d m e cha n ic al dra w in gs in f i g u r e 43, al lo ws th e desig n er t o c o n s tr uc t sim p le m e ch a n ic a l m o de ls fo r f u r t h e r a n a l y s is wi t h in t a rget e d sy st ems. table 29. mech anical properties material modulas of el a s ticity ceramic 26 10 3 kg/mm 2 kovar 14.1 10 3 kg/mm 2 tungsten 35 10 3 kg/mm 2 t h e r m o p l a s t i c 2 7 9 kg/mm 2 silicon 11 10 3 kg/mm 2 additi ona l informa t ion this da ta sh e e t p r o v ides a g e n e ral o v er view o f th e ad14060 / ad14060l a r c h i t ec t u r e an d f u nc tio n ali t y . f o r deta iled inf o r m a t io n on th e ads p -2106 x s h ar c and t h e ads p -21000 f a m i ly c o re arch ite c tu re a n d i n st r u c t i o n s e t , re f e r to t h e adsp -210 6x sh arc u ser s m a n u a l . 0.012 4x ref 0.040 0.002 0.250 0.345 0.670 4x 0.633 2.050 sq. 0.653 4x 0.616 0.302 0.260 1.780 0.018 1.890 0.005 1.810 0.005 00667-042 f i gure 42. inte rn al p a ck ag e d i m e ns i o ns d i mensions sh o w n in inc h es
ad14060/ad14060l rev. b | page 48 of 48 outline dimensions 1 0.040 (1.016) 45 77 78 154 155 231 232 308 0.015 (0.381) 45 3 places 0.025 (0.635) bsc 3.01 (76.46) 3.00 (76.20) 2.99 (75.95) 3.050 (77.47) max top view 0.160 (4.064) max 0.035 (0.889) max 2.745 (69.72) 2.730 (69.34) 2.715 (68.96) 2.062 (52.38) 2.050 (52.07) 2.038 (51.77) 0.350 (8.89) 0.340 (8.64) 0.330 (8.38) 4 2.330 (59.18) 2.300 (58.42) 2.270 (57.66) 0.101 (2.566) 0.092 (2.337) 0.083 (2.108) 1.895 (48.13) 1.890 (48.01) 1.885 (47.88) 0.007 (0.165) 0.005 (0.127) 0.004 (0.102) 0.010 (0.254) 0.008 (0.203) 0.006 (0.152) f i g u re 43. 3 08-l e a d cer a m i c q u ad f l at pack (c qfp ) (qs-30 8) di me nsio ns sho w n i n i n che s a n d ( m il lim e t e r s) ordering guide model temperature r a n g e s m d instruction rate operating v o l t a g e p a c k a g e descri p t i o n package option ad14060bf-4 ?40c to +100c n/a 40 mhz 5 v 308-le ad ceramic quad flatpack (cqfp) qs-308 ad14060lbf-4 ?40c to +100c n/a 40 mhz 3.3 v 308- lead ceramic quad flatpack (cqfp) qs-308 ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c00667C0 C 12/04(b)

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